Latest News

Today on Design-Reuse.com

Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies

Creonic, the leading provider of high-performance IP cores for ASIC and FPGA technologies, has unveiled a bold new brand identity, reaffirming its commitment ... Read

VeriSilicon Launches Ultra-Low Power OpenGL ES GPU with Hybrid 3D/2.5D Rendering for Wearables ...

VeriSilicon’s GCNano3DVG IP combines optimized hardware pipelines with a lightweight and configurable software stack to deliver efficient, low-power ... Read

Cadence to Acquire Arm Artisan Foundation IP Business

The transaction will augment Cadence’s expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface ... Read

Vertex Growth commits €10M in Dolphin Semiconductor

Vertex Growth is a growth-stage venture capital fund anchored by Vertex Holdings, a subsidiary of global investment firm Temasek. The fund is dedicated ... Read

New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks

Together with aconnic AG, Fraunhofer IPMS has developed an innovative IP core as part of the “RealSec5G” project, which combines the advantages of ... Read

Omni Design Technologies Offers 3nm, Single Core-voltage Supply Rail Process, Voltage and ...

The ODT-PVT-ULP-001C-3 provides simple and seamless integration, requiring just a single core-voltage supply and a digital interface, removing the need ... Read

Industry Expert Blogs

New Products


Integrate Embedded Security and Accelerate IC Deployment

PUFrt Secures Entire System from the Hardware Foundation
  • All-in-one Macro: Anti-fuse OTP+PUF+TRNG+Anti-tamper Shell+Controllers

Discover PUFrt

  • Enhance Security Features with Integrated Cryptographic Co-Processor

Discover PUFcc

  • Optimize System Performance with Integrated Hardware Security Module

Discover PUFhsm


Design Partner of the Week

  • Complete service scope, including IP, CoWoS design and production
  • Industry-first N3P HBM4/12G IP taped out in Mar’25
  • N3P UCIe 32G and N5 40G Low-Power IP
  • Visit GUC at tsmc NA Technology Symposium (booth : 203)

  • System-wide real-time debug & post-deployment analytics for complex SoCs
  • DEBUG: Identify & resolve errors significantly faster than traditional solutions
  • OPTIMIZE: Identify root cause of under-performance related to CPU, memory & other SoC components
  • DEPLOY: Monitor & collect data for continuous analysis and optimization
Learn more >>

This Synopsys Webinar will cover:
  • Address bifurcation challenges
  • 16X support in Gen 7
  • Enhanced latency and power efficiency

Partner with us




List your Products

Suppliers, list your IPs for free.