D&R Industry Expert Blogs

This section features posts from around the Web by authors with passion, integrity, authority, and community support in the IP / SoC industry.

Latest Posts (Last 30 Days)

	Behind the Scenes - Introducing Xiphera's Board Xiphera Blog - Kimmo Jarvinen, Xiphera Nov. 19, 2024
	Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications QuickLogic Blog - Brian Faith, Quicklogic Nov. 19, 2024
	Redefining XPU Memory for AI Data Centers Through Custom HBM4 Alphawave Semi Blog - Archana Cheruliyil, Alphawave Semi Nov. 18, 2024
	Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology? QuickLogic Blog - Brian Faith, Quicklogic Nov. 13, 2024
	Post-Quantum Cryptography: Safeguarding the Future of Digital Security Synopsys Blog - Dana Neustadter, Sara Zafar Jafarzadeh, Vincent van der Leest (Synopsys) Nov. 12, 2024
	UALink™ Shakes up the Scale-up AI Compute Landscape Cadence Blog - Arif Khan (Cadence) in collaboration with Gautam Singampalli (Cadence) Nov. 08, 2024
	Flash Forward: MRAM and RRAM Bring Embedded Memory and Applications into the Future Synopsys Blog - Daryl Seitzer, Rahul Thukral (Synopsys) Nov. 04, 2024
	Hardware-Assisted Verification: Unlocking the Future of Chip and System Design Synopsys Blog - Frank Schirrmeister, Synopsys Nov. 04, 2024
	Ensuring Quality and Providing Exceptional Support for IP Cores at Chip Interfaces Chip Interfaces Blog - Chip Interfaces Nov. 04, 2024
	A Brief on Message Bus Interface in PIPE Cadence Blog - Sanjeet Kumar, Cadence Oct. 24, 2024
	In-At-Near? The NPU Style Debate - Fairy Tale Version Quadric Blog - Quadric Oct. 24, 2024
	From TSMC A16 and Multi-Physics Flows to Photonics and AI-Driven Design Migrations: Synopsys Receives Multiple TSMC Partner of the Year Awards Synopsys Blog - Synopsys Oct. 24, 2024
	Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem Cadence Blog - Mayank Bhatnagar, Cadence Oct. 21, 2024