Tezzaron Semiconductor announces a prototype memory device with record-breaking speed: 1.3 nanosecond (ns) latency, 1 ns cycle time, and a throughput of 2 Gigabits/sec on each pin

Naperville, IL - August 18, 2003 - Tezzaron Semiconductor today announced a prototype memory device with record-breaking speed: 1.3 nanosecond (ns) latency, 1 ns cycle time, and a throughput of 2 Gigabits/sec on each pin.  The underlying technology for this device is a patented 3-transistor cell that senses changes in electrical current rather than measuring electrical voltage.  Tezzaron calls the new memory PSiRAM™ – the “PS” indicates its pseudo-static performance, and “i” is the symbol for electrical current.  The prototype is a quad data rate (QDR) device designed as a 32 Megabit device in a 2Meg x 16bit configuration.  It is designed to run at 1.2 V, but operation has also been tested at 0.8 V; at the lower voltage, the device exhibits speeds in excess of 400 MHz and power dissipation of less than 0.125 W.

Although Tezzaron is better known for 3D semiconductor technology, it also develops memory innovations.  PSiRAM™ development surged to the forefront last year with the sudden availability of a 90-nanometer manufacturing run.  This opportunity, arranged by IP supplier Virtual Silicon Technologies, was a perfect fit for a PSiRAM™ prototype.
 
The manufacturing opportunity dictated an extremely tight schedule.  Tezzaron’s engineers tackled the challenge at a breakneck pace, putting in 20-hour days, sleeping in a spare office, and working through weekends and the Christmas holidays.  “It was a super-human achievement,” says Tezzaron’s CTO, Robert Patti. “72 million transistors and more than 250 custom layouts – no standard cells – and it went from concept to tape-out in only seven weeks.  And it succeeded in first-pass silicon!  These guys are truly incredible.”

Team leader Mark Hilbert acknowledged Virtual Silicon’s valuable assistance with layout verification, and gave credit to Cadence Design Systems tools as well: “We have years of experience with these tools; the Cadence® custom design flow was a big factor.  The tool capabilities saved us a lot of time, especially with a design of this complexity.”

The PSiRAM™ prototype was built in a 90-nanometer facility, producing memory cells measuring only 0.59 square microns each.  Because PSiRAM™ uses a standard CMOS logic process, it is ideal for SoC (System on Chip) processing and development; Tezzaron intends to license PSiRAM™ technology for use in SoC applications.

Tezzaron plans full production of PSiRAM™ chips next year.  A 130-nanometer version is slated for the first half of 2004, followed by a 90-nanometer version late in the year.

Tezzaron Semiconductor is a privately funded corporation with headquarters in Naperville, Illinois, and a processing subsidiary in Singapore.  For more information, visit www.tezzaron.com.

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