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Today on Design-Reuse.com
RaaS, a collaborative initiative, adopted Menta's eFPGA technology for RaaS Edge Computing ...
Menta has delivered its best technology to the Research Association for Advanced Systems (RaaS). Read
In a significant achievement for the automotive industry, Cadence's Tensilica HiFi 5 Digital Signal Processors (DSPs) are now a key component in NXP® ... Read
SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence ...
This is the first IP from SiFive to include a highly scalable AI matrix engine, which accelerates time to market for semiconductor companies building ... Read
Partner Highlight
Intel and AWS Expand Strategic Collaboration, Helping Advance U.S.-Based Chip Manufacturing ...
Intel to Produce Custom AI Fabric Chip on Intel 18A and Custom Xeon 6 Chip on Intel 3 for AWS; Multi-Year, Multi-Billion-Dollar Collaboration Accelerates ... Read
Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that Joachim Kunkel will ... Read
Under the partnership agreement, Omni Design is providing custom, advanced Swift™ data converters, analog front-end (AFE), and supporting IP solutions. ... Read
Industry Expert Blogs
Frontgrade Gaisler Blog Fabio Malatesta, Frontgrade Gaisler
Codasip Blog Tariq Kurd, Distinguished Engineer and Lead IP Architect, Codasip
Ceva's Experts blog Elia Shenberger, Ceva
Synopsys Blog Manuel Mota, Synopsys
16bit 2Msps SAR General Purpose ADC in SMIC 40nm
Bluetooth 5.3 Dual Mode PHY
Automotive GPU with FuSa Advancement
8-stage superscalar processor that supports ISO 26262 ASIL-D ...
40G UCIe PHY for high-density advanced packages
High speed 3.3V I/0 Library with 8kV ESD protection in TPSCo ...
Low jitter, low-power clock-deskew PLL operating from 6GHz to ...
HBM4 Memory Controller
1.8V/1.0V 16-Channel 10-Bit 1MSPS ADC on Samsung 28nm
nQrux® Secure Boot - Quantum-Secure Authenticated Boot
Video Encoder IP - 4k60 Scalable up to 8K120
Internallly Compensated LDO - 100mA Output
AXI2APB Bridge
Simulation VIP for AMBA LTI
UCIe Verification IP
SPMI Verification IP
BoW Verification IP
UCIe Verification IP
Aeonic Generate Clock Generation Module [PLL], 8x smaller than ...
Industry Articles
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Proven solutions for converting a chip specification into RTL and UVM
Nikita Gulliya
Agnisys -
Revolutionizing Chip Design with AI-Driven EDA
Thomas Andersen
Synopsys -
Optimizing Automated Test Equipment for Quality and Complexity
Jeorge Hurtarte
Teradyne -
An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
Niloufar Mosharafian
Analogue Insight -
How to cost-efficiently add Ethernet switching to industrial devices
Comcores
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Optimizing Analog Layouts: Techniques for Effective Layout Matching
Abhishek BV
eInfochips -
Why Interlaken is a great choice for architecting chip to chip communications in AI chips
Chip Interfaces
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Fully Automating Chip Design
Hans Bouwmeester
PrimisAI
