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New Verification IP
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SPMI Verification IP
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
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BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
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Ethernet Preemption Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
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MIPI A-PHY Verification IP
- Supports MIPI A-PHY specification 1.0 and 1.1
- Supports single lane and dual lane, point-to-point and serial communication technology
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
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UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
Top Verification IP
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1
SPMI Verification IP
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
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2
USB4 Verification IP (VIP)
- Compliant with USB4 Specification.
- Supports USB3.2 Gen2 and Gen3 Operation.
- Support constrained randomization of protocol attributes.
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3
USB 2.0 SystemVerilog Verification IP
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4
PCI Express Verification Component
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5
Synthesizable LPDDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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6
UART 16x50 eVC
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7
Source Code Test Suites AXI Interconnect
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8
Source Code Test Suites PCIe
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9
PCIe Gen6 VIP
- Comprehensive support for PCI Express standard for 1.1, 2.1, 3.0, SR-IOV, SOP/PQI, and Intel PIPE PHY including BFMs for N-port Root Complex, Endpoint, SR-IOV Endpoint, N-port Switch, and PIPE-compliant PH
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10
PIPE 4.3 compliant PHY Verification IP
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DDR4 Memory Model
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12
HBM Verification IP
- Compliant to JEDEC HBM SDRAM Specification version JESD235.
- Supports connection to any HBM Memory Controller IP communicating with a JESD235 compliant HBM Memory Model.
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