English
ARChitect Processor Configurator: The Power of Configurable Processing At Your Fingertips
ARC International’s Patented Technology Explained
Introduction
Configurable processor technology is bringing about a revolution in the semiconductor industry. For years, SoC designers have settled for sub-optimum products from their silicon IP suppliers. This caused lost revenue as processor overkill or rigid, fixed performance parameters resulted in wasted silicon area, unneeded power drain and a lack of differentiation. Led by ARC International, configurability has come of age and is helping solve these challenges by changing the way our customers design SoCs.
Yet there still exists a common misconception in the industry that to gain these advantages, one must endure longer design cycles, increased verification tasks, and greater project risk. Those holding this misconception have not yet experienced the ease with which fully verified, application-specific processors may be configured and extended using ARC International’s patented processor configuration technology.
This paper introduces ARC International’s processor configuration technology by providing a brief history of ARC’s configuration technology, a summary of ARC’s recently awarded patent and a tour of the ARChitect™ processor configurator.
A Brief History of ARC’s Patented Technology
ARC International, established in 1998, was the pioneer in developing and introducing configurable technology to the semiconductor industry. In order to make the benefits of configurability easily accessible to SoC designers, ARC created a tool to automate the process of configuring its processor architecture.
The ARChitect processor configurator is a Java-based design tool that allows SoC designers to configure and extend an ARC processor through a graphical user interface (GUI) with drag-and-drop components, and point-and-click options that reside on the user’s desktop. The tool enables the creation of highly cost-effective cores by allowing designers to add only the features they need while deleting the features they do not need. In addition, the ARChitect tool allows designers to extend the architecture of the core by adding custom instructions, allowing further optimization of the processor for the end application.
Today, ARC International has close to 100 licensees, including key innovators in the high-volume consumer electronics market. Each of these licensees uses the ARChitect processor configurator to create customized core designs that exactly meet the needs of their specific applications. Current licensees include industry leaders such as Broadcom, Conexant, Fujitsu Microelectronics Europe, Infineon Technologies, SanDisk, Sony, TTPCom and many others.
ARC Awarded Key Patent on Configurability and Extendibility
Based on the company’s pioneering work in the field of SoC configurability and extendibility, ARC International has been awarded a key patent in the field of configurable processing. On Tuesday, March 1, 2005, ARC International was awarded patent number 6,862,563 by the United States Patent and Trademark Office. This patent, entitled “Method and Apparatus for Managing the Configuration and Functionality of a Semiconductor Design,” details processes and systems used to generate a description language model of a processor core using libraries containing prototype and extension logic descriptions, as well as user inputs relating to the desired core configuration and extension features.
A possible example of a method described by the patent is shown in this diagram:
ARChitect Processor Configurator Overview:
One practical implementation of ARC International’s patented technology is the proprietary ARChitect™ processor configurator. In addition to optimizing a design for die size, power and application performance, the ARChitect configurator provides guidelines for final silicon area and memory requirements. Included is the ability to configure features around the core such as type and size of caches, interrupts, DSP subsystem, timers and debug components, as well as features within the core such as type and size of core registers, address widths and instruction set options. Ultimately, performance and die size tradeoffs are quickly accomplished, resulting in an optimized solution. Invariably the ARC core will be smaller and lower power than non-ARC cores with fixed configurations.
The ARChitect processor configurator is a suite of tools used by SoC designers to rapidly create customized ARC processor core designs optimized for specific applications. The ARChitect tool streamlines and simplifies complete design projects, from system analysis through technology independent synthesis. Specific functions performed by ARChitect include the following:
ARChitect Configurator Makes Processor Configuration Simple
The primary interface to the ARChitect tool is the configuration GUI shown in Figure 1. Through this GUI, it is possible to configure both the internal architecture and the surrounding resources for ARC processors. Project builds are initiated with templates for specific types of processing: General Purpose Processor, DSP, Minimal, etc. From there, features such as caches, debug features, peripherals, optional instructions, DSP features, MMU, etc. (see tabs on the left side of figure 1) can be dragged and dropped onto the processor to add that feature. Further customization also can be achieved by selecting each component added to the processor and varying configurable features from pull down menus. (see menu on the right hand side of figure 1).
Figure 1:
As these selections are being made, guidance on system parameters such as required memory and approximate gate count impact are available immediately through the tabs at the top of the block diagram window in figure 1.
The desired configuration can be reached in a matter of minutes. Once the processor is configured, the build button at the top of the ARChitect tool window is pressed, and a fully functional Verilog® source code implementation is stitched together with the selected configuration. At this point, the designer has everything he would receive from the delivery of a fixed processor core, except the ARC processor is tailored to his exact specifications.
ARChitect Configurator Enables Low Risk Processor Extendibility
Extendibility in processor cores is a process by which designers can use spare or unused resources in the processor’s base architecture to define their own customized resources. In other words, spare op codes and register addresses can be assigned application specific functionality by the designer. Significant gains in application efficiency can be achieved by defining these custom processor architecture extensions.
The ARChitect configurator has a four-step extension wizard, which makes the process of adding instructions, registers and other logic easy to do and eliminates the risks of introducing bugs into the processor logic. The extension wizard is flexible and allows the creation of complex interactions between custom registers, ALUs, and condition codes. This dramatically reduces the number of cycles required to execute inner loops and other critical code segments. The result is higher application performance and/or much lower device frequency and power than can be achieved with fixed-architecture cores.
Stage 1 of the extension wizard simply requires the designer to name the new instruction and create a short description of it that is used by the ARChitect tool’s help functions.
Figure 2: Extension Wizard Stage 2 - Template Selection
In Stage 2 of the extension wizard, the designer selects the type of resources this instruction will include. Templates for ALU instructions, condition codes, core registers, and auxiliary registers may be selected. A single type may be selected for simple extensions, and multiples of each type could be selected for more complex extensions. For each template added, options such as op code number, number of operands, number of cycles to execute, register address, etc are added to fields in the wizard. The templates and field entry ensure that 100% compliant control and structural code are supplied by the extension wizard. Only the customer-specific logic needs to be added by the customer.
Figure 3: Extension Wizard Stage 3 – Customer Logic Insertion
Stage 3 of the extension wizard is the stage in which the customer Verilog (or System C) code is added to the extension. All the available inputs, outputs, and external signals available to the designer are shown in the tables at the bottom of this page of the wizard. Then the designer simply adds the logic for the extension between the ARCPRAGMA statements in the text editor at the top of the page. Because the logic is added in industry standard Verilog or System C, there is no need for the designer to learn any new input languages. Also, the exact code entered will be recognizable to the designer in the final processor source code.
The fourth and final stage of the GUI allows the designer to add functional verification code to exercise the instruction during regression testing. This code is input as assembly code and will automatically be added to the regression suite of any ARChitect build that includes that custom extension.
At the conclusion of the final stage, the extension wizard creates a fully compliant ARChitect library element that can be configured onto any ARC processor by selecting the extension and dragging it onto the processor as shown in Figure 1. The extension wizard also creates extensions to the Instruction Set Simulator (ISS), Cycle Accurate Simulator (CAS), and files to include with software builds to instruct the compiler to be able to use the extension. All of these are created from a single input (Verilog or System C) to ensure consistency between implementation and design tools.
ARChitect Configurator Optimizes Downstream Development Process
The last two sections have shown how easy the ARChitect tool makes the process of generating processor RTL that is uniquely tailored to a particular application through configurability and extendibility. But the value of the ARChitect tool does not stop with RTL generation. The output of every ARChitect build contains resources that will be used to reduce the design cycle in every phase of the project.
Simulation and Test Bench: The output of each ARChitect build contains a test bench for the unique processor configuration. The test bench includes a suite of targeted, self-checking assembly code and the resources to execute that code right out of the box. This code fully exercises the functionality of the core and exhaustively tests the interfaces to the core. A full suite of scripts for the targeted simulator are created, so standalone regression can be run with a single ARCtest command. These scripts and test code can be easily adapted to system level tests to ensure verticality of test environments and to accelerate development of system verification environments.
Synchronization of Software Tools: The ability to create unique processor extensions is of little use if they are not available and understood by the software development tools. ARChitect configurator ensures that the configuration of the processor is communicated to the compiler so it can take advantage of the resources in the build. It also ensures that the ISS and CAS are extended with the customer’s unique extensions created by the extension wizard, and that the compiler understands these new instructions.
FPGA Emulation Builds: To further accelerate system testing and software development, ARChitect configurator enables system level emulation with the exact same RTL as will be used in the final SoC product. By selecting FPGA target in the ARChitect system page, a full set of Synplicity scripts targeting the Xilinx FPGA on the ARCangel FPGA emulation system will be produced. Any build can quickly be reduced to the Xilinx.xbf file by simply typing ARCsyn in a command line. This creates the ability to do very high frequency software development emulation, and “what if” testing of different configurations. These scripts also enable rapid translation of the ARC processor RTL into other, customer specific FPGA emulation boards.
Synthesis Scripts: When the processor build is ready to start system synthesis, the same approach used for FPGA emulation is available to target any custom chip libraries. The system parameter in the ARChitect tool is switched from FPGA to ASIC and then the scripts are created for Synopsys all the way through Physical Compiler gate placement. Automatic compiling and stitching in of physical RAM models also is supported for some technologies to further accelerate the synthesis process.
Documentation Generation: The ARChitect tool even accelerates the often tedious task of documenting the processor. The memory map, full instruction suite, full register set, interrupt structure etc…, are created as .html files for inclusion into SoC specifications, and even to include in user guide’s for ARC licensee’s customers. This also reduces the time investment in completing the project.
Subsystem Delivery: As ARC moves forward with the development of fully integrated hardware and software subsystems such as the ARCsound audio subsystem and upcoming video products, the ARChitect tool will be just as instrumental in delivering to the customer exactly what they need for their application. In these subsystems, ARC already has optimized the processor configuration and created extensions to deliver peak performance to the customer. This hardware configuration will be delivered as a template in the ARChitect configurator. These subsystems also include fully tested software (MP3, AAC, MPEG-4, H.264, etc) to run on these configurations. The ARChitect configurator also allows the required codecs to be selected and delivered alongside the hardware to ensure synchronization between the optimized hardware and software releases.
Conclusion
By enabling the easy creation of optimized solutions, ARC International’s patented processor configuration technology is fueling the industry trend toward configurable and extendible processing. Industry leaders who have standardized on ARC’s configurable technology are getting their innovations to market faster and more cost-effectively than ever before. As configurable processing continues to solve significant design challenges, the ARChitect processor configurator is truly placing the power of configurability at the fingertips of today’s SoC designers.
Information detailed in this white paper is subject to change. The ARC logo, ARC, ARChitect, ARCtangent, ARCompact, ARCsound, MetaSim and MetaWare are trademarks or registered trademarks of ARC International. ARC International recognizes other brand and product names as trademarks or registered trademarks of their respective owners.
www.ARC.com
Introduction
Configurable processor technology is bringing about a revolution in the semiconductor industry. For years, SoC designers have settled for sub-optimum products from their silicon IP suppliers. This caused lost revenue as processor overkill or rigid, fixed performance parameters resulted in wasted silicon area, unneeded power drain and a lack of differentiation. Led by ARC International, configurability has come of age and is helping solve these challenges by changing the way our customers design SoCs.
Yet there still exists a common misconception in the industry that to gain these advantages, one must endure longer design cycles, increased verification tasks, and greater project risk. Those holding this misconception have not yet experienced the ease with which fully verified, application-specific processors may be configured and extended using ARC International’s patented processor configuration technology.
This paper introduces ARC International’s processor configuration technology by providing a brief history of ARC’s configuration technology, a summary of ARC’s recently awarded patent and a tour of the ARChitect™ processor configurator.
A Brief History of ARC’s Patented Technology
ARC International, established in 1998, was the pioneer in developing and introducing configurable technology to the semiconductor industry. In order to make the benefits of configurability easily accessible to SoC designers, ARC created a tool to automate the process of configuring its processor architecture.
The ARChitect processor configurator is a Java-based design tool that allows SoC designers to configure and extend an ARC processor through a graphical user interface (GUI) with drag-and-drop components, and point-and-click options that reside on the user’s desktop. The tool enables the creation of highly cost-effective cores by allowing designers to add only the features they need while deleting the features they do not need. In addition, the ARChitect tool allows designers to extend the architecture of the core by adding custom instructions, allowing further optimization of the processor for the end application.
Today, ARC International has close to 100 licensees, including key innovators in the high-volume consumer electronics market. Each of these licensees uses the ARChitect processor configurator to create customized core designs that exactly meet the needs of their specific applications. Current licensees include industry leaders such as Broadcom, Conexant, Fujitsu Microelectronics Europe, Infineon Technologies, SanDisk, Sony, TTPCom and many others.
ARC Awarded Key Patent on Configurability and Extendibility
Based on the company’s pioneering work in the field of SoC configurability and extendibility, ARC International has been awarded a key patent in the field of configurable processing. On Tuesday, March 1, 2005, ARC International was awarded patent number 6,862,563 by the United States Patent and Trademark Office. This patent, entitled “Method and Apparatus for Managing the Configuration and Functionality of a Semiconductor Design,” details processes and systems used to generate a description language model of a processor core using libraries containing prototype and extension logic descriptions, as well as user inputs relating to the desired core configuration and extension features.
A possible example of a method described by the patent is shown in this diagram:
ARChitect Processor Configurator Overview:
One practical implementation of ARC International’s patented technology is the proprietary ARChitect™ processor configurator. In addition to optimizing a design for die size, power and application performance, the ARChitect configurator provides guidelines for final silicon area and memory requirements. Included is the ability to configure features around the core such as type and size of caches, interrupts, DSP subsystem, timers and debug components, as well as features within the core such as type and size of core registers, address widths and instruction set options. Ultimately, performance and die size tradeoffs are quickly accomplished, resulting in an optimized solution. Invariably the ARC core will be smaller and lower power than non-ARC cores with fixed configurations.
The ARChitect processor configurator is a suite of tools used by SoC designers to rapidly create customized ARC processor core designs optimized for specific applications. The ARChitect tool streamlines and simplifies complete design projects, from system analysis through technology independent synthesis. Specific functions performed by ARChitect include the following:
- Selection of configuration options through an easy to use GUI
- Integration of customer IP through a simple extension wizard
- Generation of simulation scripts and test benches for system verification
- Synchronization of software development tools with the customized processor
- Automated generation of FPGA builds for the ARCangel™ emulation platform
- Generation of synthesis scripts for incorporation into SoC level scripts
- Delivery of integrated subsystem hardware and software IP for system level products
- Documentation of selected configuration for inclusion in licensees’ chip specifications and customer level documentation
ARChitect Configurator Makes Processor Configuration Simple
The primary interface to the ARChitect tool is the configuration GUI shown in Figure 1. Through this GUI, it is possible to configure both the internal architecture and the surrounding resources for ARC processors. Project builds are initiated with templates for specific types of processing: General Purpose Processor, DSP, Minimal, etc. From there, features such as caches, debug features, peripherals, optional instructions, DSP features, MMU, etc. (see tabs on the left side of figure 1) can be dragged and dropped onto the processor to add that feature. Further customization also can be achieved by selecting each component added to the processor and varying configurable features from pull down menus. (see menu on the right hand side of figure 1).
Figure 1:
As these selections are being made, guidance on system parameters such as required memory and approximate gate count impact are available immediately through the tabs at the top of the block diagram window in figure 1.
The desired configuration can be reached in a matter of minutes. Once the processor is configured, the build button at the top of the ARChitect tool window is pressed, and a fully functional Verilog® source code implementation is stitched together with the selected configuration. At this point, the designer has everything he would receive from the delivery of a fixed processor core, except the ARC processor is tailored to his exact specifications.
ARChitect Configurator Enables Low Risk Processor Extendibility
Extendibility in processor cores is a process by which designers can use spare or unused resources in the processor’s base architecture to define their own customized resources. In other words, spare op codes and register addresses can be assigned application specific functionality by the designer. Significant gains in application efficiency can be achieved by defining these custom processor architecture extensions.
The ARChitect configurator has a four-step extension wizard, which makes the process of adding instructions, registers and other logic easy to do and eliminates the risks of introducing bugs into the processor logic. The extension wizard is flexible and allows the creation of complex interactions between custom registers, ALUs, and condition codes. This dramatically reduces the number of cycles required to execute inner loops and other critical code segments. The result is higher application performance and/or much lower device frequency and power than can be achieved with fixed-architecture cores.
Stage 1 of the extension wizard simply requires the designer to name the new instruction and create a short description of it that is used by the ARChitect tool’s help functions.
Figure 2: Extension Wizard Stage 2 - Template Selection
In Stage 2 of the extension wizard, the designer selects the type of resources this instruction will include. Templates for ALU instructions, condition codes, core registers, and auxiliary registers may be selected. A single type may be selected for simple extensions, and multiples of each type could be selected for more complex extensions. For each template added, options such as op code number, number of operands, number of cycles to execute, register address, etc are added to fields in the wizard. The templates and field entry ensure that 100% compliant control and structural code are supplied by the extension wizard. Only the customer-specific logic needs to be added by the customer.
Figure 3: Extension Wizard Stage 3 – Customer Logic Insertion
Stage 3 of the extension wizard is the stage in which the customer Verilog (or System C) code is added to the extension. All the available inputs, outputs, and external signals available to the designer are shown in the tables at the bottom of this page of the wizard. Then the designer simply adds the logic for the extension between the ARCPRAGMA statements in the text editor at the top of the page. Because the logic is added in industry standard Verilog or System C, there is no need for the designer to learn any new input languages. Also, the exact code entered will be recognizable to the designer in the final processor source code.
The fourth and final stage of the GUI allows the designer to add functional verification code to exercise the instruction during regression testing. This code is input as assembly code and will automatically be added to the regression suite of any ARChitect build that includes that custom extension.
At the conclusion of the final stage, the extension wizard creates a fully compliant ARChitect library element that can be configured onto any ARC processor by selecting the extension and dragging it onto the processor as shown in Figure 1. The extension wizard also creates extensions to the Instruction Set Simulator (ISS), Cycle Accurate Simulator (CAS), and files to include with software builds to instruct the compiler to be able to use the extension. All of these are created from a single input (Verilog or System C) to ensure consistency between implementation and design tools.
ARChitect Configurator Optimizes Downstream Development Process
The last two sections have shown how easy the ARChitect tool makes the process of generating processor RTL that is uniquely tailored to a particular application through configurability and extendibility. But the value of the ARChitect tool does not stop with RTL generation. The output of every ARChitect build contains resources that will be used to reduce the design cycle in every phase of the project.
Simulation and Test Bench: The output of each ARChitect build contains a test bench for the unique processor configuration. The test bench includes a suite of targeted, self-checking assembly code and the resources to execute that code right out of the box. This code fully exercises the functionality of the core and exhaustively tests the interfaces to the core. A full suite of scripts for the targeted simulator are created, so standalone regression can be run with a single ARCtest command. These scripts and test code can be easily adapted to system level tests to ensure verticality of test environments and to accelerate development of system verification environments.
Synchronization of Software Tools: The ability to create unique processor extensions is of little use if they are not available and understood by the software development tools. ARChitect configurator ensures that the configuration of the processor is communicated to the compiler so it can take advantage of the resources in the build. It also ensures that the ISS and CAS are extended with the customer’s unique extensions created by the extension wizard, and that the compiler understands these new instructions.
FPGA Emulation Builds: To further accelerate system testing and software development, ARChitect configurator enables system level emulation with the exact same RTL as will be used in the final SoC product. By selecting FPGA target in the ARChitect system page, a full set of Synplicity scripts targeting the Xilinx FPGA on the ARCangel FPGA emulation system will be produced. Any build can quickly be reduced to the Xilinx.xbf file by simply typing ARCsyn in a command line. This creates the ability to do very high frequency software development emulation, and “what if” testing of different configurations. These scripts also enable rapid translation of the ARC processor RTL into other, customer specific FPGA emulation boards.
Synthesis Scripts: When the processor build is ready to start system synthesis, the same approach used for FPGA emulation is available to target any custom chip libraries. The system parameter in the ARChitect tool is switched from FPGA to ASIC and then the scripts are created for Synopsys all the way through Physical Compiler gate placement. Automatic compiling and stitching in of physical RAM models also is supported for some technologies to further accelerate the synthesis process.
Documentation Generation: The ARChitect tool even accelerates the often tedious task of documenting the processor. The memory map, full instruction suite, full register set, interrupt structure etc…, are created as .html files for inclusion into SoC specifications, and even to include in user guide’s for ARC licensee’s customers. This also reduces the time investment in completing the project.
Subsystem Delivery: As ARC moves forward with the development of fully integrated hardware and software subsystems such as the ARCsound audio subsystem and upcoming video products, the ARChitect tool will be just as instrumental in delivering to the customer exactly what they need for their application. In these subsystems, ARC already has optimized the processor configuration and created extensions to deliver peak performance to the customer. This hardware configuration will be delivered as a template in the ARChitect configurator. These subsystems also include fully tested software (MP3, AAC, MPEG-4, H.264, etc) to run on these configurations. The ARChitect configurator also allows the required codecs to be selected and delivered alongside the hardware to ensure synchronization between the optimized hardware and software releases.
Conclusion
By enabling the easy creation of optimized solutions, ARC International’s patented processor configuration technology is fueling the industry trend toward configurable and extendible processing. Industry leaders who have standardized on ARC’s configurable technology are getting their innovations to market faster and more cost-effectively than ever before. As configurable processing continues to solve significant design challenges, the ARChitect processor configurator is truly placing the power of configurability at the fingertips of today’s SoC designers.
Information detailed in this white paper is subject to change. The ARC logo, ARC, ARChitect, ARCtangent, ARCompact, ARCsound, MetaSim and MetaWare are trademarks or registered trademarks of ARC International. ARC International recognizes other brand and product names as trademarks or registered trademarks of their respective owners.
www.ARC.com
Related Articles
- Choosing the right low power processor for your embedded design
- Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO
- Calibrate and Configure your Power Management IC with NVM IP
- A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
- Right-Sizing Your Cryptographic Processing Solution
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
|
E-mail This Article | 
|
|
Printer-Friendly Page |