How FPGA packaging drives signal integrity

As speeds increase, bit periods shrink, reducing the available timing margins. Today's memory interfaces run at greater than 500Mbps per line with rise times in the hundreds of picoseconds. This creates a substantial signal integrity challenge for the FPGA designer.

As interfaces get wider and faster, simultaneously switching output noise (SSN) grows in severity. SSN adds to the system jitter, eating into the timing margin and affecting system performance. In the worst case, SSN can cross the logic threshold, causing the system to malfunction altogether.

Good package design is critical to good noise performance in FPGAs. This article describes the package design considerations with a focus on signal integrity and its impact on system performance.

The role of the package

Historically, short signal paths have not altered signal characteristics because speeds were still fairly low. Today, with rise times in the hundreds of picoseconds (even if bit periods are few nanoseconds), the frequency components of signals run into GHz, causing even very short signal paths like package traces to impact signals.

For every signal line there is an associated return path for the return currents. For single-ended signals, these return paths are usually GND or VCC reference planes. To maintain a 50-Ohm line the returns should be in close proximity to the signal.

While PCB traces are less of a concern, designers must pay close attention to vias. For large FPGAs the breakout region — the area between the package balls to the PCB — is extremely critical since it comprises a dense concentration of signal vias.

SSN is generally observed as "ground bounce" and can be caused by two different phenomena:

Package and PCB via-field crosstalk. Noise due to via-field crosstalk is a function of the loop inductance, which is a function of the proximity of ground/power reference pin locations to the signal pin. Signal pins that are farther away from a reference pin are more susceptible to noise.

This problem is exacerbated when a number of I/Os in the region switch simultaneously. Hence proper distribution of ground/power and signal pins in a package is extremely critical — in other words, a good pinout architecture.

Compromised power integrity due to high package inductance. Maintaining a clean power supply to the FPGA is critical to maintain acceptable signal integrity. Noise margins are reduced as VCC values drop down to 1.2v in the latest FPGAs.

Further, any noise in the power rail translates to jitter at the output, shrinking the available timing margins as well. As noise depends on package inductance and number of simultaneously switching I/Os (L.di/dt), optimal signaling requires a good low-inductance package.

Tackling the SSN challenge

One package that tackles the SSN challenge is the Xilinx Virtex-4 FPGA package with the SparseChevron Pinout Architecture. Most notably, the package enables better noise performance on higher-speed, single-ended interfaces which are more susceptible to noise than differential interfaces such as LVDS.

Pinout architecture
The pinout architecture of the package is responsible for roughly 80% of the total noise. The Virtex-4 FPGA package achieves optimal pin distribution through a tiled pattern — a regular array of signal, ground and power pins called SparseChevron pinout (Figure 1).

The signal-to-ground-to power ratio of the package is 8:1:1. Since both power and ground are equally effective as return current paths, the package effectively has a signal-to-return ratio of 4:1. Also, the pins are distributed so that every signal pin is adjacent to a return pin, ensuring that the return current loop is kept to a minimum.

Figure 1 — SparseChevron pinout

Additionally, the abundance of return paths in any given area of the package provides a low impedance path for the return currents. The pinout also confines noise from an aggressor to a smaller area so the influence of the aggressor drops rapidly with distance. Since crosstalk noise is cumulative, this results in a lower total SSN.

Power plane integrity
There are several reasons why the power and ground planes are important to maintaining signal integrity in FPGA designs. In order to maintain the characteristic impedance (Z_o) across the frequency range of interest, reference planes for single-ended signals need to be very low impedance.

Otherwise, the result is impedance discontinuities causing jitter due to reflections. In addition, noisy power and ground planes affect the circuit performance on the die causing additional jitter. It is important to design packages with continuous power and ground planes to minimize impedance.

Typically, PCB designers use decoupling capacitors to filter out noise and maintain a clean power supply. For reducing high frequency noise, decoupling capacitors are placed close to the noise source. Leading edge ASICs and FPGAs such are equipped with very low-inductance decoupling capacitors within the package to aid cleaning the power supply noise.

Other important considerations
Some pins such as voltage reference and clocks are crucial to the overall performance of the chip. Any noise on these pins propagates to large sections of circuitry on the die. It is critical to minimize/isolate the noise on these pins through proper spacing of the signals within the package.

Package performance — a case study

Third party lab measurements show that the noise performance of the new Xilinx Virtex-4 package is 4X-7X lower than traditional offerings. Figure 1 also shows the noise measurements for 500 I/Os switching simultaneously with I/Os configured for 8mA LVCMOS. The noise was measured on a "victim" pin programmed to a logic-1 or a logic-0.

The SSN performance of each pin is very much a function of location. Every signal pin in the SparseChevron package has at least one reference PWR/GND pin adjacent to it, so there is no "bad pin" for crosstalk. For the test, the "victim" pin along the edge where there are fewer adjacent reference pins was chosen as the worst case scenario.

Summary

Signal integrity is an important factor in system design, with parallel interfaces getting faster and wider. A well designed package is a crucial component to the noise performance. All leading edge chip vendors need to wake up to this reality and incorporate innovative technologies into their package design.

Panch Chandrasekaran is connectivity marketing manager at Xilinx Inc.