SOI eases radiation-hardened ASIC designs

Historically, rad-hard applications have not been able to step up to the latest technologies and silicon manufacturing processes. High gate counts and associated high clock speeds represent a dramatic change for rad-hard electronics.

Advancements in rad-hard ASIC technology are required because the latest non-hardened commercial ICs still exhibit errors and reliability problems when exposed to radiation environments. Radiation phenomena such as single event effects occur in space applications, in aircraft at high altitudes, and even in terrestrial environments.

Specialized SOI fabrication and appropriate libraries and tools provide embedded protection against these radiation hazards. While higher-level techniques such as triple/majority voting and error-correction codes may be necessary for some applications, embedded protections built into the silicon process and design flow provide a highly effective foundation for radiation tolerance or radiation hardening.

For applications ranging from military/aerospace to implanted medical electronics, the hardening techniques address the reliability, signal integrity, parameter shifts and single-event upsets associated with various types of radiation (Table 1).

Table 1 — Radiation sources, impact, and mitigation

Radiation hardness can be built into the IC at several levels with little effort on the part of designer. The first level is the silicon-on-insulator (SOI) process that provides safeguards against many radiation effects and can be modified to handle others.

The second level of hardening is within the cell libraries, where radiation protection is enhanced by specific design practices and physical design. The third level is related to ASIC design implementation and is supported by the ASIC design process and software tools.

Silicon on insulator advantages

SOI offers many inherent advantages by using a thin film of silicon on top of an insulator. While bulk CMOS relies on junction isolation between devices, SOI uses dielectric isolation to surround the entire device sides and bottom. SOI has no wells into the substrate and therefore has no latchup or leakage paths.

These advantages simplify fabrication steps, improve density and reduce parasitic capacitance. The result is up to 30 percent lower power consumption, 20 percent higher performance and 15 percent higher density than traditional bulk CMOS at the same feature size.

While this article cannot describe every type of radiation effect, it is useful to consider some of the more critical effects as examples of SOI's benefits. For instance, SOI inherently eliminates latchup, which can occur in CMOS devices due to a parasitic condition in which at least one PNP and at least one NPN transistor act like a silicon controlled rectifier (SCR) if turned on in a prompt dose or single event upset (SEU) event.

This parasitic PNPN structure creates a low-impedance path between the power rails and can permanently damage the device. Because the wells in an SOI device are completely oxide isolated, the parasitic SCR effect cannot occur.

In contrast to commercial SOI, radiation-sensitive devices require hardening of the buried oxide and trench isolation. Without this hardening, charge induced by gamma rays can get trapped over time in the buried oxide, then recombine next to the oxide/silicon interface and change a device's threshold voltage. The SOI structure can be built to provide places where charge can recombine away from the oxide/silicon interface.

Another example of SOI's benefits is its inherent resistance to SEUs. In general, a heavy ion can cause an SEU by scattering charge (holes and electrons) along its path as it passes through a device. When holes and electrons recombine, the resulting current pulse can cause a change in state of a memory element such as a latch or SRAM bit. SOI's charge collection volume is 10 times less than that of bulk silicon, so SOI is far less likely to experience bit-switching current pulses.

These inherent advantages can be improved upon by fabricating a connection to the body of a device that provides a place for ion charges to go to ground. This structure contrasts with most commercial SOI processes, which use a floating body and are less SEU resistant. Commercial SOI generally avoids the body tie because it imposes a 30 percent area penalty, but hardened SOI technology can substantially reduce this penalty with specialized techniques.

Design hardening

Radiation resistance can be enhanced with several hardening methods for the ASIC library and design flow. Library cells address radiation performance on several levels, including cell designs, special simulation models and unique layout techniques.

To improve SEU resistance, for example, key library cells (such as flip-flops and latches) can include specialized structures that introduce enough delay to keep the circuit from switching state before ion charges can recombine. With these types of structures in the ASIC library, no intervention by designers is necessary.

High photo-currents associated with prompt dose radiation can cause transient IR drop on power busses, and some circuits are sensitive to the currents generated within the cell. These issues can have impacts ranging from temporary functional failure to loss of memory data and even permanent damage to the part. For radiation hardened libraries, these issues are mitigated through careful cell design combined with guidelines for power bussing and packaging.

Radiation hardening encompasses many other design practices that affect every part of the design flow. During RTL design verification, for example, designers must make sure that all state machines have default recovery states (no "don't-care" clauses).

In synthesis and timing analysis, extra timing margin helps ensure that radiation-induced parametric shifts will not cause errors. Long term, total-dose radiation effects may cause changes in timing performance — typically less than 10 percent for hardened technologies.

Clocks and reset paths deserve special care because of their global effects on the design. Some designs may require resets to ensure a known state for all devices. With asynchronous resets, an SEU-induced spike can cause multiple flip-flops to change state.

The synchronous approach forces the reset logic into the data pin of the flip-flop and allows redundant logic or techniques applied within the flip-flop (described earlier) to filter out the spike. Design guidelines for these types of paths must be followed to mitigate the associated risk.

Finally, for design hand-off, the design must be checked for compliance with the foundry-specific design guidelines. The fabrication process can furnish a great deal of hardening, but the design must follow the guidelines to take full advantage of this capability. To ensure compliance, the design flow must include rigorous design and hand-off reviews.

Packaging

Military ASICs have traditionally been packaged in a hermetically sealed, wire-bond-style package with up to 380 unique signal I/Os.

As the number of gates increases, so does the need for higher-I/O packages. One alternative is the commercial technology of flip-chip packaging. This packaging meets mil/aero requirements for electrical performance, higher I/O count and other considerations for VDSM, high-gate-count ASICs.

The flip-chip package enables a chip to be mounted face down, in contrast to the face-up approach used in traditional wire-bond packaging. With face-down mounting, inductance for all signals, power and ground are all reduced, providing better performance in transient-radiation environments.

Advanced rad-hard ASICs

By coupling an advanced SOI fabrication process with hardened standard cell libraries and a highly automated design flow, radiation-hardened ASICs can be produced with performance comparable to that of commercial-grade parts.

Honeywell and Synopsys offer such a capability, utilizing Honeywell's 150-nm SOI technology and hardened ASIC library along with Synopsys tools and design infrastructure. As Honeywell and Synopsys Professional Services have shown through their technology partnership, designing radiation hardening into the process, library and design flow frees ASIC designers to focus on the chip's functionality while still achieving the hardening required for radiation-sensitive applications.

Thomas Romanko has over 20 years experience in military, space and commercial electronics with Honeywell including 8 years experience in ASIC development. He is currently an Applications Engineer at Honeywell Defense and Space Electronic Systems (DSES) supporting the Space/Military Microelectronics product line.

Brian Clegg has 17 years of design experience in the mil/aero industry and is currently a Synopsys Professional Services consultant working with customers to develop best practices for design flows.