English
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
Programmable System Chips: An alternative to MCU-based designs?
| |
Programmable System Chips: An alternative to MCU-based designs? End applications continue to demand increased flexibility, configurability and performance, along with reduced power demands, board space and cost. To address the increasing pressure for integration and flexibility of analog, memory, logic and MCU implementations in a single chip, analog, microcontroller (MCU) and ASIC suppliers are moving to add configurability to their product lines. In addition to increased functionality, these suppliers are looking to reduce their own development costs. The skyrocketing mask costs that continue to limit ASIC product developments also impact MCU and analog suppliers with their broad product catalogs. The ability to add programmability or configurability enables semiconductor suppliers to service the same application space with significantly fewer mask sets, thereby reducing their own development time and costs. When considering four technologies: MCU, analog, ASIC and FPGA, there is a premium on FPGA programmable elements. As the rarest of the four technologies, there are several barriers to developing successful FPGAs technology. Only a handful of successful FPGA suppliers exist in the market today; of the five largest, two have a one-percent market share. FPGA technology development requires significant investment in both hardware and software. Hardware silicon requirements include the development of an efficient, flexible and high-performance programmable fabric. Extensive software tools are needed to support design development, verification, validation and programming. Unlike FPGA IP, ASIC libraries are available from any foundry. A wide variety of MCU cores are obtainable for license. Several companies have successful businesses in this space, the best known of which is ARM. Analog IP can also be sourced from several suppliers or developed in-house.
By Rich Howell, Product Marketing Manager, Flash Products, Actel Corporation, Courtesy of Programmable Logic DesignLine
Aug 10 2005 (13:12 PM)
URL: http://www.embedded.com/showArticle.jhtml?articleID=168600522
Three Key Elements
There are three key elements to making programmable system chip (PSC) a reality. The first is process technology; next is system design organization; and finally, tools support.
Process technology differences represent a substantial hurdle to integrating memory, analog and programmable logic on to a single monolithic die. Traditionally, next-generation process geometry is developed with a standard CMOS process. Driven by the need for high gate counts to implement large programmable logic solutions, many CMOS FPGA suppliers are on the leading edge of the CMOS process curve. This CMOS process, however, is not well suited for embedded flash and analog integration. It is this limitation that prohibits standard CMOS products from becoming effective programmable system chips. Typically, process support for embedded flash and analog components is several process nodes behind leading-edge CMOS nodes, resulting in a process gap between leading edge, high gate-count devices and analog- and flash-based devices.
Many analog components interface to real world sensors or power supplies. Real world signals are not limited to the 1.2V transitions of today's 90-nm CMOS process technologies. The optimal PSC process will support direct connection to these signals. By supporting higher voltages, an advanced flash process will also increase the dynamic range of the integrated analog IP. This increased dynamic range enables higher signal-to-noise ratios and improved analog performance. To help reduce noise injected into the analog IP by the high-speed digital logic, the embedded flash process must effectively isolate the analog and digital domains. This process must also support high-performance RAM and logic capabilities.
Flash-based FPGAs must handle high voltages for programming and be well isolated to keep voltages controlled. High voltage transistors enable high dynamic range and direct connect to high-voltage signals for analog IP. In addition, the triple-well process provides increased design isolation between analog and digital components and aggressive cost-effective monolithic die size development. Hence, this advanced embedded flash process would be the best technology for real-world PSC applications.
A key advantage to the PSC is a time-to-market (TTM) advantage it offers relative to mixed-signal ASIC development or a complex multi-chip solution. To ensure this TTM advantage is maximized, system design must be well organized and allow the user to develop and design at very high or very low levels of abstraction. The flexibility that PSC technology offers to system designers can be illustrated using stack of design abstraction layers analogous to the familiar and somewhat parallel OSI communications stack.
This layered model offers a flexible design environment enabling design at very high and very low levels of abstraction. There are four layers in the PSC stack. Level 0 is analogous to the Physical layer and includes hard analog intellectual property (IP) and hard and/or soft digital IP. Level 1 controls communication to and between level 0 components similar to the data link layer. Level 2 acts much like the OSI presentation layer by bringing the data up to a point where the end system application, Level 3, can act on it similar to the Application layer.
Level 0, Peripherals (Physical layer), are configurable functional blocks that can be hard-wired structures, such as a PLL (phase locked loop) or analog input channel, or implemented in soft gates, such as a UART or PC interface. The peripherals are configurable and support a standard interface to facilitate communication and implementation.
Level 1, Backbone (Link layer), connects and controls access to peripherals. This should be a soft gate structure, scalable to any number of peripherals. The backbone is bus and control logic; it manages peripheral configuration to ensure proper operation. Leveraging a common peripheral interface and a low-level state machine, the backbone efficiently off-loads peripheral management from the system design. The backbone can set and clear threshold flags based upon peripheral behavior and defined performance criteria. The flexibility of the stack enables a system designer to configure peripherals directly, bypassing the backbone if that level of control is desired.
Level 2, Applets (Presentation layer), are independent application building blocks implementing specific functions that are built in FPGA gates and using flash and analog peripherals. Applets react to stimuli and board-level events communicated via the backbone. They respond to these stimuli by accessing and manipulating peripherals via the backbone or initiating other actions. As a complete reusable IP structure, applets are easily imported into or exported from the design environment. A designer can build a complex design rapidly by importing a number of different Applets into their design.
Level 3, the System Application (Application layer) is the larger user application that uses one or more applets. Designing at the highest level of abstraction supported by the PSC Technology stack, an entire FPGA system design can be created without any HDL coding. Implemented in FPGA gates, the application can be easily created by importing and configuring multiple applets.
An optional soft MCU core enables a combination of software- and HDL-based design methodologies. System portioning is very flexible, allowing the MCU to reside above the applets or to absorb applets or applets and backbone if desired.
The PSC technology stack offers an example of a very flexible design environment. This type of organization allows users the maximum flexibility in design from very high-level pick-and-click design allowing rapid application development, to very low-level design maximizing design control, and various levels in between.
Tool support
Integration of tools for a complex PSC raises new complexity and new requirements. Some of the key required tool features at this level are:
- High level of design productivity
- New methods for rapid application generation
- Hardware / software co-verification
- Bus-based communication
- Device/system modeling and design partitioning
- Innovative debugging capability
These new tools must allow designers to easily instantiate and configure peripherals within a design, establish links between peripherals, create or import building blocks or reference designs, and perform hardware/software verification. This tools suite should also add a comprehensive hardware/software debug capability, and a suite of utilities to simplify development of embedded soft processor-based solutions (e.g., ARM and 8051).
PSC tool sets must offer users the flexibility to approach system modeling in both hardware and/or software design. Design engineers and architects have the freedom to partition their applications on FPGA logic gates, in software executed by an optional soft processor or through a judicious combination of both.
Design creation tools must offer a very flexible environment with many options. Any number of applets can be imported into the design environment, limited only by FPGA logic resources. Supported by graphic user interfaces (GUIs), these applets can be instantiated into the design and the various peripherals, configured all with the click of a mouse and without the need for HDL coding. Simultaneously, the tool chain creates the backbone, connects the required peripherals, and creates control for the desired low-level processing. All of this is done as a background activity with no direct user guidance required. These GUI-based tools focus on ease-of-use and offer rapid design development. They do not preclude traditional HDL code development for users who are more comfortable with this flow, and need to wring out every last gate for their design, or need maximum design customization.
Due to added complexity and unprecedented integration of PSC technology, simulation will play a critical role in design verification. Mixed-signal components can be modeled behaviorally in digital logic and verified in the digital environment. PSC tool solutions must provide a full suite of digital behavioral simulation models, providing simulation support for all on chip resources. This strategy significantly reduces tooling cost by eliminating the need for expensive analog modeling tools often have a $100K price tag, while allowing for meaningful system level simulation. The RTL created by the user or by application generators should pass seamlessly through logic and physical synthesis.
The unprecedented integration offered by PSC technology poses significant challenges for in-silicon design verification. Innovative debugging tools are needed for design verification at various levels of application abstractions in the stack. For example, users should be able to embed a logic analyzer into the desired blocks within the application, enabling real-time probe. It should also be possible to interface these analyzers to the backbone and monitor the activity of peripherals in real time. Furthermore, additional debug capability should enable users to access and modify configurations related to peripherals, register files, embedded SRAM and flash memory.
As PSC platforms lend themselves to embedded processing solutions, support for popular cores, such as the 8051 and ARM7, is necessary to enable the broadest range of applications. Tools will help users build applications in C that are efficient and optimized for soft MCU targets on PSC devices. Users can debug their program code with the help of software debuggers and can also perform instruction set simulation in a co-simulation environment.
An open design environment is optimal for the design community. This fosters the development of a technology ecosystem where customers, user groups, third-party tool developers and design houses come together and interact. Having each member focus on their core competency creates a very efficient, low-cost development environment. System designers will be able to capitalize on a robust support ecosystem populated by many different communities. PSC technology and design development environment enables design at a very high level of abstraction within which users easily import and export applets. These modular and well-defined applets facilitate IP reuse and sharing. Customers can develop applets that can easily be mixed, matched and shared internally to support their own application. Third-party tool suppliers can also create applet generators suited to particular vertical market applications, or use models and then distribute the applet generators as part of their tool chain, enabling rapid design developm ent. Further, combined with the vibrant processor/microcontroller ecosystem, system designers will be able to work with multiple solution providers.
Summary
Companies across many technology areas are pursuing the development of the programmable system chip (PSC). Due to the barriers inherent to developing efficient, easy-to-use, cost-effective programmable logic, FPGAs suppliers are better positioned to develop a PSC solution. The development of an advanced flash process technology, optimal for PSC, has been a major hurdle to the development of PSCs. Design organization is critical to realize the benefits of reduced TTM and development costs.
A development environment modeled after the OSI communications stack offers many advantages to a wide breadth of the PSC users. The model allows for traditional digital designers to engage at the very low (bit) level where they are accustomed. Non-traditional FPGA designers can design at a higher level by importing and configuring applets. Those familiar to embedded processor design can engage with their familiar C code and do it all in software. The model also provides a flexible and structured means of utilizing this unprecedented level of integration, facilitating IP reuse and rapid design development. Development tools must provide robust system level support while maintaining flexibility to accommodate the varying needs of the PSC user base.
About the Author
Richard Howell is a product line manager, handling the Actel Fusion product and a member of the flash product marketing team at Actel Corp. Howell received a Bachelor degree in physics and Masters’ degrees in engineering management and business administration from California Polytechnic State University in San Luis Obispo. Richard can be reached at rich.howell@actel.com
Copyright 2005 © CMP Media LLC
Related Articles
- Interfacing High Performance 32-bit Cores To MCU-based Memory Architectures
- Embedded Systems: Programmable Logic -> Programmable system chips 'fly' high
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- Optimizing Designs Through System Simulation
- Upgrading 8- and 16-bit MCU designs: Development ecosystem
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
|
E-mail This Article | 
|
|
Printer-Friendly Page |