Tips for maximizing RapidIO
Travis Scheckel
(10/03/2005 10:00 AM EDT)
RapidIO is an open, standards-based interconnection technology for midsize and large embedded systems. It enables packet-switched, peer-to-peer connections among ASICs, DSPs, FPGAs, microprocessors, network processors and backplanes, with speeds of up to 60 Gbits/second, depending on how it's implemented.
Here are eight tips for designers working with RapidIO for the first time:
- Port where possible. RapidIO can be implemented on existing backplanes without significantly modifying hardware, and it works with existing technologies, such as 0.18- and 0.25-micron CMOS systems. RapidIO also supports parallel and serial connections, so designers can quickly and easily port their parallel RapidIO products to a serial environment in order to produce a new line of semiconductors and ASICs.
- Bridge with caution. RapidIO includes bridging functions so that it can work with other bus technologies, such as PCI and PCI Express, and with system-area networks such as Infiniband. But be aware of potential trade-offs.
- Consider dc coupling. The serial RapidIO spec supports ac coupling but doesn't rule out dc coupling as an option. Designers can save the cost of coupling caps and biasing resistors in many cases by opting for dc coupling.
- Watch the clock. To meet the RapidIO spec's bit error rate goals, most serdes vendors have stringent requirements for the reference clocks. These aren't basic clock sources; supported reference clock frequencies will vary depending on vendor.
- Design for speed. To avoid bottlenecks, overprovision the fabric/link speed. A lot of work has been done on implementing congestion control in fabrics.
- Know your devices' limits. Not all devices support all of RapidIO's data rates. Also, the link rates aren't automatically negotiated; the system integrator must program them at boot time.
- Deactivate retry. Some applications are more tolerant of packet loss, so they prefer that method over packet retries. RapidIO gives designers the option of deactivating the retry mechanism in applications that involve time-sensitive data. Just check to make sure that the devices support the retry-deactivation feature.
- Check the extensions. The RapidIO spec includes several extensions that designers should study to maximize their applications. For more information about flow control and other extensions, see www.rapidio.org/about/RapidFabric.
Travis Scheckel (t-scheckel@ti.com), wireless infrastructure systems engineer for Texas Instruments Inc.
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |