English
Routing density analysis of ASICs, Structured ASICs, and FPGAs
By Zvi Or-Bach, eASIC Corp
Programmable Logic DesignLine
(10/19/2005 11:14 AM EDT)
This article uses well-known routing estimation techniques to analyze the trends of routing area requirements for standard cell ASICs, coarse-grained standard metal Structured ASICs, and field programmable gate arrays FPGAs. The cell granularity and the metal interconnect structure of these diametrically different architectures is analyzed and compared.
Standard cell ASICs typically feature fine-grained cell architectures. These devices have functions created out of standard single gate primitives, which are combined with custom metal interconnect, metal segments, and vias fabricated with custom masks. At the other end of the spectrum we find FPGAs, which are standard products with programmable elements that are used to connect predefined metal segments together with coarse-grained programmable cells.
Programmable Logic DesignLine
(10/19/2005 11:14 AM EDT)
This article uses well-known routing estimation techniques to analyze the trends of routing area requirements for standard cell ASICs, coarse-grained standard metal Structured ASICs, and field programmable gate arrays FPGAs. The cell granularity and the metal interconnect structure of these diametrically different architectures is analyzed and compared.
Standard cell ASICs typically feature fine-grained cell architectures. These devices have functions created out of standard single gate primitives, which are combined with custom metal interconnect, metal segments, and vias fabricated with custom masks. At the other end of the spectrum we find FPGAs, which are standard products with programmable elements that are used to connect predefined metal segments together with coarse-grained programmable cells.
Structured ASICs have regular arrays of coarse-grained programmable cells. Early Structured ASIC fabrics required multiple unique metal and via photomasks to fully implement a design. More recently, standard metal Structured ASICs have evolved. These devices comprise a sea of basic logic and memory building blocks coupled with a pre-configured, pre-characterized routing superhighway system. In the case of these standard metal fabrics, a single via layer - implemented using a single photomask or ebeam - is used to turn different routing paths on and off.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis
- Improving ASIC Design Verification using FPGAs and Structured ASICs
- FPGAs and Structured ASICs: Low-Risk SoC for the Masses
- FPGAs and Structured ASICs: Low-Risk SoC for the Masses
- Hybrid process converts FPGAs to structured ASICs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)