English
Blistering traffic speeds: a detailed look inside PCI Express
Steve Kolokowsky and Trevor Davis, Cypress Semiconductor
Oct 24, 2005 (10:48 PM)
CommsDesign
PCI Express is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, based on a much faster serial communications system. In fact, PCI Express is a scalable bus that provides as little as 250Mbytes/second at a 2.5Ghz signaling rate up to 8Gbytes/second in the first spec revision. Higher bandwidths can be achieved by increasing clock speed or bus width.
This technology, like many other bus protocols, uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry information from a transmitting component to a receiving component (See Figure 1). As transmitted packets flow through each layer, they are modified to contain additional information necessary to handle packets at those layers
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow