How to adapt traditional RTOSes to symmetric multiprocessing
Embedded.com, Dec 12 2005 (9:00 AM)
Mulltiprocessor (MP) and multicore System-on-Chip architectures are now beginning to be employed in a wide range of embedded consumer and communications systems. They are perceived as a way to enhance performance in applications requiring execution of multiple tasks without the demands on power consumed in a single processor configuration cranked up to its highest clock rate.
Typical of such applications are a set-top box designed to record several channels while sharing home movies across the Internet, or an in-car computer system doing navigation tasks while at the same time delivering backset video gaming, anong others.
But MP designs introduce programming complexity that can make them difficult to use and can threaten development schedules. Better software tools are needed to make MP development easier, and included among them is the operating system, which – when properly implemented -- has the unique capability of enabling an MP system to be programmed much like a single processor system.
But to make this possible, commercial providers of RTOSes - and the 50 percent or so of all developers who still build their own real time operating kernels - are faced with significant challenges. As the shift is made to more diverse, heterogeneous multiprocessing, the big questions facing developers include: what changes will have to be made to the applications developed for such environments, to the tools and the underlying OS structure.
It is clear that as designs with six, seven or more processing elements on a chip emerge, significant changes will have to be made. However, currently there is a large class of embedded applications in consumer electronics that allow the use of the well known symmetric multiprocessing (SMP) approach. Developed for server clusters and large computing applications, SMP does not require significant changes to the seasoned sequential, procedural single programming model.
When chosen with careful attention to real time performance, multithreading and real time interrupt response, even existing RTOSes can be used in such environments, While it will not be possible to achieve the theoretical maximum performance of an n-CPU device in a multiprocessor configuration (n*100%), significant incremental improvements are possible, ranging from 20% to even 90% under ideal conditions.
Related Articles
- Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm
- How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
- Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
- How to cost-efficiently add Ethernet switching to industrial devices
- How to Turbo Charge Your SoC's CPU(s)
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- An Outline of the Semiconductor Chip Design Flow
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Synthesis Methodology & Netlist Qualification
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |