English
How to make your asymmetric multiprocessor design OS and CPU independent
By Francis St. Amant , Polycore Software Inc.
Dec 21 2005 (1:42 AM), Embedded.com
Even as semiconductor companies tend toward multiprocessing solutions in many network as well as embedded consumer and mobile designs, the RTOSes and development tools are still rushing to catch up with the shift.
Most multiprocessing-capable operating systems support one type of processor at a time and are often limited to symmetric multiprocessing (SMP). While SMP provides a relatively straightforward path from single processing, it can only be used for homogeneous configurations with shared resources.
But most embedded applications are at least partially asymmetric in nature. And asymmetric multiprocessor (AMP) systems require multiple instantiations of the same or different operating systems running on different cores.
In a system with different OSes or a heterogeneous multicore system, implementing a common middleware structure to manage communications between the processors comes down to bridging between the different OSes and/or processor types.
Many of the first generation multiprocessor designs currently in consumer embedded systems, fortunately, are not complicated and it has been possible to incorporate simple, often hand-coded, communications mechanisms to synchronize operation. But such designs will not scale well and are not portable to the next generation of three, four, six and eight core configurations that are emerging.
What is needed is a way to organize all the system software modules necessary for inter-core communications into a framework transparent to the operating system or platform (hardware and logical).
Dec 21 2005 (1:42 AM), Embedded.com
Even as semiconductor companies tend toward multiprocessing solutions in many network as well as embedded consumer and mobile designs, the RTOSes and development tools are still rushing to catch up with the shift.
Most multiprocessing-capable operating systems support one type of processor at a time and are often limited to symmetric multiprocessing (SMP). While SMP provides a relatively straightforward path from single processing, it can only be used for homogeneous configurations with shared resources.
But most embedded applications are at least partially asymmetric in nature. And asymmetric multiprocessor (AMP) systems require multiple instantiations of the same or different operating systems running on different cores.
In a system with different OSes or a heterogeneous multicore system, implementing a common middleware structure to manage communications between the processors comes down to bridging between the different OSes and/or processor types.
Many of the first generation multiprocessor designs currently in consumer embedded systems, fortunately, are not complicated and it has been possible to incorporate simple, often hand-coded, communications mechanisms to synchronize operation. But such designs will not scale well and are not portable to the next generation of three, four, six and eight core configurations that are emerging.
What is needed is a way to organize all the system software modules necessary for inter-core communications into a framework transparent to the operating system or platform (hardware and logical).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)