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Process Detector (For DVFS and monitoring process variation)
Using dual port interconnect to resolve multiprocessor system bottlenecks
By Jonathan LaRue and Danny Tseng, Cypress Semiconductor
Jan 18 2006 (12:00 PM), Embedded.com
The use of two or more specialized off-the-shelf processors has provided designers with tremendous computing capabilities and speed. With this growing multiple processor trend, however, comes the need for a high-performance system interconnect to bridge the gap between varying data rates, bus widths and I/O standards.
Additionally, on-board traffic management becomes an issue in many data intensive applications and the last thing designers need is a system interconnect that causes a dataflow bottleneck. The use of high speed dual-ports adds value to any design through its blazing data rates (up to 36 Gb/sec), versatile application in a system, and simple implementation using existing standard memory interfaces.
Jan 18 2006 (12:00 PM), Embedded.com
The use of two or more specialized off-the-shelf processors has provided designers with tremendous computing capabilities and speed. With this growing multiple processor trend, however, comes the need for a high-performance system interconnect to bridge the gap between varying data rates, bus widths and I/O standards.
Additionally, on-board traffic management becomes an issue in many data intensive applications and the last thing designers need is a system interconnect that causes a dataflow bottleneck. The use of high speed dual-ports adds value to any design through its blazing data rates (up to 36 Gb/sec), versatile application in a system, and simple implementation using existing standard memory interfaces.
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