English
How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications
Mingliang Liu, Lava Technologies
Feb 21, 2006 (2:05 PM), CommsDesign
Since the VCO is one of the most important elements in the PLL system it is an appropriate place to begin this article, which addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop (PLL) for wireless LAN applications. The design assumes a specific process, namely TSMC 0.35 micron technology.
The schematic of the VCO is shown in Figure 1. Transistors M8 and M9 form a NMOS cross-coupled differential pair to provide the negative resistance, which is required for generating an oscillation. M0, M1 and R3 form the biasing network for the oscillator. L7 and C8 form the filtering network to suppress the high frequency noise generated by the bias current source.
Related Articles
- How to make virtual prototyping better than designing with hardware: Part 1
- How to make virtual prototyping better than designing with hardware: Part 2
- How to make virtual prototyping better than designing with hardware: Part 1
- How to design an Interlaken to SPI-4.2 bridge
- MPEG-4 system layer and A/V containers for wireless video
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow
|
E-mail This Article | 
|
|
Printer-Friendly Page |