English
Implementing H.264 video compression algorithms on a software configurable processor
By Frank Lee, Stretch, Inc.
Mar 10 2006 (9:00 AM), Embedded.com
The significant coding efficiency of H.264 video compression technology opens a wide range of new applications for streaming video over a variety of media.
This international standard has risen in importance with its recent adoption by 3G, DVD Forum, and DVB, joining MPEG-2 as one of the world’s most common digital video formats. The H.264 standard provides advanced algorithms for motion estimation, inter-prediction, spatial intra prediction and transforms. The H.264 standard supports motion estimation on blocks from 16x16 to 4x4 pixels.
Residual data transforms are executed on 4x4 blocks with modified integer discrete cosine transform (DCT) which avoids rounding errors. In common with other standards, such as MPEG, the H.264 codec implementation is not explicitly defined.
The standard defines the syntax of the encoded bit stream and the method for decoding the bitstream. Developers of H.264 require a development methodology that enables experimentation and refinements of their algorithms and the ability to deliver a real-time encoding of the video.
Keeping pace with Moore’s law, today’s CPUs continue to be massively powerful, but their architectures are not well suited for video processing. One approach has been to augment the CPU with hardware acceleration units called intrinsic instructions (such as Intel’s MMX/SSE2 and AMD’s 3DNow extensions). Acceleration hardware can be designed to support the block-based and pixel-level processing tasks that are not efficiently handled by the CPU architecture.
However, many of the core encoding tasks, such as motion estimation etc., which consume many CPU cycles, are also very dataflow intensive, thus requiring deep register pipelines with fast memory accesses. Traditionally this has been best met with a purely hardware approach. This paper will describe the design methodology and the results of using a single 300MHz software configurable processor to achieve H.264 encoding of Standard Definition (SD) video at 30 fps.
Mar 10 2006 (9:00 AM), Embedded.com
The significant coding efficiency of H.264 video compression technology opens a wide range of new applications for streaming video over a variety of media.
This international standard has risen in importance with its recent adoption by 3G, DVD Forum, and DVB, joining MPEG-2 as one of the world’s most common digital video formats. The H.264 standard provides advanced algorithms for motion estimation, inter-prediction, spatial intra prediction and transforms. The H.264 standard supports motion estimation on blocks from 16x16 to 4x4 pixels.
Residual data transforms are executed on 4x4 blocks with modified integer discrete cosine transform (DCT) which avoids rounding errors. In common with other standards, such as MPEG, the H.264 codec implementation is not explicitly defined.
The standard defines the syntax of the encoded bit stream and the method for decoding the bitstream. Developers of H.264 require a development methodology that enables experimentation and refinements of their algorithms and the ability to deliver a real-time encoding of the video.
Keeping pace with Moore’s law, today’s CPUs continue to be massively powerful, but their architectures are not well suited for video processing. One approach has been to augment the CPU with hardware acceleration units called intrinsic instructions (such as Intel’s MMX/SSE2 and AMD’s 3DNow extensions). Acceleration hardware can be designed to support the block-based and pixel-level processing tasks that are not efficiently handled by the CPU architecture.
However, many of the core encoding tasks, such as motion estimation etc., which consume many CPU cycles, are also very dataflow intensive, thus requiring deep register pipelines with fast memory accesses. Traditionally this has been best met with a purely hardware approach. This paper will describe the design methodology and the results of using a single 300MHz software configurable processor to achieve H.264 encoding of Standard Definition (SD) video at 30 fps.
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