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How to reduce simultaneous switching output noise with a stand-alone SerDes
LVCMOS outputs from an FPGA are unsuited for driving over long interconnects or at high data rates.
By Lee Sledjeski, National Semiconductor
A critical issue with any Field Programmable Gate Array (FPGA) design is Simultaneous Switching Output (SSO) noise. SSO noise, also known as ground bounce, is a result of large instantaneous changes in current across the power/ground inductance of the integrated circuit. This potential problem becomes more serious as the number of active high-drive LVCMOS outputs on a FPGA design increases. In large FPGAs with several synchronous parallel interfaces this phenomenon can result in poor system performance or intermittent data errors.
An external Serializer/Deserializer (SerDes) used in conjunction with minimum current drive FPGA I/O can reduce an FPGA's internal noise and receive the benefits of a serial interface across the system. This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have high analog performance.
Using the lowest drive current from the FPGA and reducing the parallel bus to a single differential signal minimize the SSO noise. LVCMOS outputs from the FPGA are unsuited for driving over long interconnects or at high data rates. Upgrading the parallel interfaces with an external SerDes interface to the FPGA reduces SSO noise and improves the overall system performance. The close proximity of the external SerDes to the FPGA allows FPGA I/O to be programmed at the minimum CMOS drive level of about 2 mA. Reducing the drive level lowers the dynamic currents within the FPGA curbing the generation of SSO noise. Noise generated in the I/Os on a FPGA can corrupt the analog performance of FPGA PLLs or other system analog resources.
The Altera "Cyclone" or Xilinx "Spartan" families are good examples of economical FPGAs intended for low to medium speed applications. They do not contain dedicated serialization or deserialization circuitry for high-speed communications limiting the maximum data rate to 640 Mbps. This makes the Cyclone and Spartan good candidates for an external serial interface. Using a SerDes external to an FPGA allows an entire multi-byte parallel interface to be condensed to one or more high-speed signal pairs.
By Lee Sledjeski, National Semiconductor
A critical issue with any Field Programmable Gate Array (FPGA) design is Simultaneous Switching Output (SSO) noise. SSO noise, also known as ground bounce, is a result of large instantaneous changes in current across the power/ground inductance of the integrated circuit. This potential problem becomes more serious as the number of active high-drive LVCMOS outputs on a FPGA design increases. In large FPGAs with several synchronous parallel interfaces this phenomenon can result in poor system performance or intermittent data errors.
An external Serializer/Deserializer (SerDes) used in conjunction with minimum current drive FPGA I/O can reduce an FPGA's internal noise and receive the benefits of a serial interface across the system. This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have high analog performance.
Using the lowest drive current from the FPGA and reducing the parallel bus to a single differential signal minimize the SSO noise. LVCMOS outputs from the FPGA are unsuited for driving over long interconnects or at high data rates. Upgrading the parallel interfaces with an external SerDes interface to the FPGA reduces SSO noise and improves the overall system performance. The close proximity of the external SerDes to the FPGA allows FPGA I/O to be programmed at the minimum CMOS drive level of about 2 mA. Reducing the drive level lowers the dynamic currents within the FPGA curbing the generation of SSO noise. Noise generated in the I/Os on a FPGA can corrupt the analog performance of FPGA PLLs or other system analog resources.
The Altera "Cyclone" or Xilinx "Spartan" families are good examples of economical FPGAs intended for low to medium speed applications. They do not contain dedicated serialization or deserialization circuitry for high-speed communications limiting the maximum data rate to 640 Mbps. This makes the Cyclone and Spartan good candidates for an external serial interface. Using a SerDes external to an FPGA allows an entire multi-byte parallel interface to be condensed to one or more high-speed signal pairs.
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