English
Facilitating System-in-Package (SiP) design
Keith Felton (Cadence Design Systems) and Jamie Metcalfe (Optimal Corp)
(06/05/2006 4:46 PM EDT), EE Times
In the latest move in the cost, density, and time-to-market battles, a number of wireless and consumer-focused IC and systems companies are turning to System-in-Package (SiP) design to gain a competitive advantage. Hemmed in, on the one hand, by the technical challenges of producing compact, high-performance, multi-function products and, on the other, by a fast-moving, competitive marketplace, they are scrambling to reduce every cent in product cost and every hour spent in design.
To this end, SiP design offers clear advantages — more function in less space and reduced design cycle times. But to deliver on the promise of SiP design, EDA software providers have to develop tools with new functionality and present scalable design methods and flows.
An ideal solution will give SiP design team members the ability to create die abstracts in an IC environment, RF design in an IC and substrate design environment, and package/board co-design in an integrated packaging/PCB design environment.
(06/05/2006 4:46 PM EDT), EE Times
In the latest move in the cost, density, and time-to-market battles, a number of wireless and consumer-focused IC and systems companies are turning to System-in-Package (SiP) design to gain a competitive advantage. Hemmed in, on the one hand, by the technical challenges of producing compact, high-performance, multi-function products and, on the other, by a fast-moving, competitive marketplace, they are scrambling to reduce every cent in product cost and every hour spent in design.
To this end, SiP design offers clear advantages — more function in less space and reduced design cycle times. But to deliver on the promise of SiP design, EDA software providers have to develop tools with new functionality and present scalable design methods and flows.
An ideal solution will give SiP design team members the ability to create die abstracts in an IC environment, RF design in an IC and substrate design environment, and package/board co-design in an integrated packaging/PCB design environment.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)