English
Process Detector (For DVFS and monitoring process variation)
The need for verification management
Ilana Golan, Cadence Design Systems
(06/05/2006 9:00 AM EDT), EE Times
Project management and automation are quickly becoming the most critical elements of the design and verification process. The key ingredients are good specification development and metric-based checkpoints. The ability to "begin with the end in mind" allows for optimal resource usage, much higher design quality and realistic schedule estimates for customers.
Today's design and verification flows often miss cross-functional problems. The flows tend to focus primarily on individual tasks, engine performance or languages, rather than on defining the entire verification challenge or team interdependencies. In fact, most verification plans are merely a set of incomplete discussion notes that atrophy as the project moves forward.
Good management of the design and verification process starts with specific goals that focus on what needs to be verified. Using those guidelines, an experienced verification team can develop and implement a plan that includes everything. Stakeholders can capture and review the verification plan to drive the design safely and smoothly to closure.
Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind.
(06/05/2006 9:00 AM EDT), EE Times
Project management and automation are quickly becoming the most critical elements of the design and verification process. The key ingredients are good specification development and metric-based checkpoints. The ability to "begin with the end in mind" allows for optimal resource usage, much higher design quality and realistic schedule estimates for customers.
Today's design and verification flows often miss cross-functional problems. The flows tend to focus primarily on individual tasks, engine performance or languages, rather than on defining the entire verification challenge or team interdependencies. In fact, most verification plans are merely a set of incomplete discussion notes that atrophy as the project moves forward.
Good management of the design and verification process starts with specific goals that focus on what needs to be verified. Using those guidelines, an experienced verification team can develop and implement a plan that includes everything. Stakeholders can capture and review the verification plan to drive the design safely and smoothly to closure.
Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- A need for static and dynamic Low Power Verification
- SoC technology underscores need for verification
- Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification
- PCI Express verification underscores need to plan
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- An Outline of the Semiconductor Chip Design Flow
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Synthesis Methodology & Netlist Qualification