System-on-chip bulk CMOS can cause a paradigm shift
Dr. Jonathan Cheah and Jennifer Ayers, Jaalaa Inc.
Jun 12, 2006 (5:00 AM), CommsDesign
As the total cost gap closes between wireless systems made of discrete components and wireless system-on-chip (SoC) solutions, the time has come to consider trading traditional pcb and discrete device solutions for fully-integrated silicon designs. The paradigm shift from the traditional pcb and its multiple discrete systems circuits to a single silicon substrate changes the product design concepts, design flow, key resources, and the nature of the development and product cycle.
In the last five years, logic bulk CMOS processes have replaced RF CMOS processes for the mass production of mixed-signal SoCs. Many of these products produced using bulk CMOS processes operate in high frequencies such as the common 2.4-GHz ISM band and the increasingly common 5.7-GHz band. The success of these bulk CMOS high-frequency mixed-signal designs has sparked further advancement. For example, SoCs incorporating all components—the RF transceiver, CPU, ROM, RAM, and necessary product interfaces—have emerged.
Complete SoC integration initially required a large-volume market to make economic sense, and Bluetooth cellular headsets were the first major integrated wireless product to have this. Size, weight, and dc power constraints of these headsets necessitated complete product-on-chip integration. All functional blocks needed for product integration outside of the Bluetooth core were integrated into the same silicon substrate. These blocks include the dc-to-dc converter, the audio codec, and audio amplifiers suitable for driving the miniature speaker.
Rarely in consumer electronics has a complete wireless communications system been implemented with a specific product in mind. In this case, the silicon substrate fulfilled all the roles the pcb and discrete components usually play. The pcb is just a structural extension of the plastic enclosure, used as a chip carrier and to accommodate noise-decoupling capacitors (Fig. 1).
E-mail This Article | Printer-Friendly Page |
Related Articles
- Single core to multicore: Addressing the system design paradigm shift with project management and software instrumentation
- Case study of a complex video system-on-chip
- A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
- Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment
- DPCI: An Efficient Scalable System-on-chip Communication Architecture
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)