English
SystemVerilog reference verification methodology: ESL
Thomas Anderson, Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale
(06/12/2006 9:00 AM EDT)
Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL). While the level of abstraction required to verify the design has risen correspondingly, at every stage verification has remained a major challenge. In today’s system-on-chip (SoC) design world, a wide range of verification techniques must be linked by a reuse-oriented, coverage-driven verification methodology for effective usage.
This is the third in a series of four articles outlining a reference verification methodology that covers both RTL and system-level requirements. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on the techniques recommended by the VMM for SystemVerilog for ESL verification.
(06/12/2006 9:00 AM EDT)
Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL). While the level of abstraction required to verify the design has risen correspondingly, at every stage verification has remained a major challenge. In today’s system-on-chip (SoC) design world, a wide range of verification techniques must be linked by a reuse-oriented, coverage-driven verification methodology for effective usage.
This is the third in a series of four articles outlining a reference verification methodology that covers both RTL and system-level requirements. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on the techniques recommended by the VMM for SystemVerilog for ESL verification.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- SystemVerilog Reference Verification Methodology: VMM Adoption
- SystemVerilog reference verification methodology: RTL
- SystemVerilog reference verification methodology: Introduction
- System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study
- Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Reference Verification Methodology (RVM)
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)