English
Design and verification strategies for complex systems, part 1
Increasing complexity and shrinking schedules push designers to use new methodologies
By Graham Hellestrand, Founder, CTO, and Strategy Officer, VaST Systems Technology
Embedded system architectures increasingly feature multi-processor configurations with large numbers of independent buses and bus-bridges. Conventional design and verification strategies are not capable of meeting business and technical objectives at this level of complexity.
In the first part of this series, we highlight trends in embedded system design. We then review conventional embedded design and verification techniques, and explain the tradeoffs associated with each approach. In the second part of the series, we will present and discuss the concept of architecture-driven design using virtual system prototyping.
By Graham Hellestrand, Founder, CTO, and Strategy Officer, VaST Systems Technology
Embedded system architectures increasingly feature multi-processor configurations with large numbers of independent buses and bus-bridges. Conventional design and verification strategies are not capable of meeting business and technical objectives at this level of complexity.
In the first part of this series, we highlight trends in embedded system design. We then review conventional embedded design and verification techniques, and explain the tradeoffs associated with each approach. In the second part of the series, we will present and discuss the concept of architecture-driven design using virtual system prototyping.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Design and verification strategies for complex systems: Part 2
- Verification = IP = Verification = IP… - Part 1: Current Industry Situation and Drivers
- An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
- Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained
- Where Innovation Is Happening in Geolocation. Part 1: Signal Processing
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology