English
Design and verification strategies for complex systems: Part 2
By Graham Hellestrand, Founder, CTO, and Strategy Officer, VaST Systems Technology
In the first part of this series, we highlighted trends in embedded system design and explained the shortcomings of conventional design and verification techniques. In this article, we present and discuss the concept of architecture-driven design using virtual system prototypes.
Virtual system prototypes
A virtual system prototype is a type of electronic systems level (ESL) model that can be thought of as a hybrid between an RTL model and an ISS model. (See part 1 for descriptions of RTL and ISS models.) Like an RTL model, a virtual system prototype is cycle-accurate and can be used to simulate and develop hardware. However, a virtual system prototype is based on software simulation, like an ISS model, and simulates at speeds suitable for software development. A virtual system prototype can be used to represent portions of an embedded system or the entire system. Virtual prototype environments are available from companies such as VaST Systems Technology (www.VaSTsystems.com), Synopsys (www.Synopsys.com), and ARM (www.ARM.com).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Design and verification strategies for complex systems, part 1
- Verification = IP = Verification = IP =... - Part 2 (By Dr. Aart de Geus)
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
- Specifying a PLL Part 2: Jitter Basics
- Part 2: Opening the 5G Radio Interface
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)