English
Reducing cycle times for design rule checking
James Paris, Mentor Graphics Corp.
(07/31/2006 9:00 AM EDT), EE Times
Design rule checking (DRC) is the gold standard in the hand-off of IC designs to the manufacturer. From the beginning, when newly developed physical verification tools automated the manual check method, a DRC-clean design was the most accurate ticket to yield. Based on a compliance method of pass/no pass, the system was simple and straightforward, giving designers a faster method of sign-off and measurable assurance for successful silicon.
But at 130nm node, DRC-clean designs began failing first silicon. At that time, it became obvious that the compliance process required more than pass/no pass. This didn't mean DRC was no longer a valid process for sign-off; it did mean, however, that DRC would have to evolve. Robust verification tools began to do just that, managing design-for-manufacturing capabilities, such as antennae effects, stress effects, metal fill and via insertion.
But that was just the beginning of the evolution. For the upcoming nanometer nodes of 65nm and 45nm, the DRC engine is revving up for a whole new race.
(07/31/2006 9:00 AM EDT), EE Times
Design rule checking (DRC) is the gold standard in the hand-off of IC designs to the manufacturer. From the beginning, when newly developed physical verification tools automated the manual check method, a DRC-clean design was the most accurate ticket to yield. Based on a compliance method of pass/no pass, the system was simple and straightforward, giving designers a faster method of sign-off and measurable assurance for successful silicon.
But at 130nm node, DRC-clean designs began failing first silicon. At that time, it became obvious that the compliance process required more than pass/no pass. This didn't mean DRC was no longer a valid process for sign-off; it did mean, however, that DRC would have to evolve. Robust verification tools began to do just that, managing design-for-manufacturing capabilities, such as antennae effects, stress effects, metal fill and via insertion.
But that was just the beginning of the evolution. For the upcoming nanometer nodes of 65nm and 45nm, the DRC engine is revving up for a whole new race.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Casting a wide safety net through post processing Checking
- Reducing Power Hot Spots through RTL optimization techniques
- Reducing Debug time for Scan pattern using Parallel Strobe Data (PSD) Flow
- Formal Property Checking for IP - A Case Study
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)