English
Virtual prototyping speeds mixed-signal IC design
Raja Mitra, Cadence Design Systems
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Top-down approach speeds mixed-signal design
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-Signal Verification for USB 2.0 Physical Layer IP
- Building High-Quality, Mixed-Signal IP in 65-nm and Beyond
- Mixed-signal FPGAs provide GREEN POWER
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow