English
USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
How to get the best cost savings when implementing an FPGA-to-ASIC conversion
By Harald Wyndham, AMIS
September 06, 2006 -- pldesignline.com
Planning an FPGA-to-ASIC conversion requires that the ASIC vendor is involved as early as possible in order to achieve the best cost savings.
Many key decisions effecting cost reduction through conversion of an FPGA to an ASIC are often made by people who may not be giving it much thought at the time. The R&D team tasked with program board development, and the FPGA designers and component engineers who support them can often times give little consideration to approaches that would make the board more "ASIC friendly." Cost reduction through conversion / integration of FPGA's and other components can be a second-order concern at that point, when the primary focus is proof of concept and when high production volumes may seem far in the future. However, ASIC vendors need to be involved early in the customer's design process – while the board designer and FPGA engineer are still in the concept phase – to give advice and provide training that can broaden the options for cost reducing to an ASIC from a manufacturing standpoint.
This article will discuss how the ASIC vendor can assist the OEM board design and FPGA design teams in "designing for portability," so that their strategies for power supplies, package types, I/O utilization, IP selection and the development of timing scripts and clocking architectures can be developed with consideration of maximizing cost reduction through conversion to ASIC. Additionally, it will discuss the strategies ASIC and structured ASIC designers should consider to assure first time success of their designs in silicon and a smooth transition from prototype approval to volume production of reliable, cost-effective devices.
September 06, 2006 -- pldesignline.com
Planning an FPGA-to-ASIC conversion requires that the ASIC vendor is involved as early as possible in order to achieve the best cost savings.
Many key decisions effecting cost reduction through conversion of an FPGA to an ASIC are often made by people who may not be giving it much thought at the time. The R&D team tasked with program board development, and the FPGA designers and component engineers who support them can often times give little consideration to approaches that would make the board more "ASIC friendly." Cost reduction through conversion / integration of FPGA's and other components can be a second-order concern at that point, when the primary focus is proof of concept and when high production volumes may seem far in the future. However, ASIC vendors need to be involved early in the customer's design process – while the board designer and FPGA engineer are still in the concept phase – to give advice and provide training that can broaden the options for cost reducing to an ASIC from a manufacturing standpoint.
This article will discuss how the ASIC vendor can assist the OEM board design and FPGA design teams in "designing for portability," so that their strategies for power supplies, package types, I/O utilization, IP selection and the development of timing scripts and clocking architectures can be developed with consideration of maximizing cost reduction through conversion to ASIC. Additionally, it will discuss the strategies ASIC and structured ASIC designers should consider to assure first time success of their designs in silicon and a smooth transition from prototype approval to volume production of reliable, cost-effective devices.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
