ARM11 MPCore Provides Existing Software Portability Across Single- CPU and Multi-CPU Designs

by Erik Ploof, ARM

Abstract:

The ARM11 MPCore synthesizable processor implements the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to an aggregate 2600 Dhrystone MIPS of performance. The ARM11 MPCore processor provides enhanced memory throughput of 1.3 Gbytes/sec from a single CPU, and a solution that delivers greater performance at lower frequencies than comparable single processor designs, offering significant cost savings to system designers, while maintaining full compatibility with existing EDA tools and flows. It also simplifies otherwise complex multiprocessor design, reducing time-to-market and total design cost.

The ARM11 MPCore™ synthesizable multiprocessor supports the popular ARM11™ microarchitecture with the ability to scale up to four CPUs from a single synthesis instantiation. With high performance, simplified multi-processor design and flexible software support, the ARM11 MPCore is an ideal processor across a broad range of solutions in consumer, networking and mobile markets.

Using the ARM11 MPCore with one CPU provides a streamlined and efficient processor for solutions requiring high memory throughput in a core area in 130 nm as low as 2.7 mm2 (including integrated system peripherals).

The ARM11 MPCore enables solutions to scale to include additional processors with full data cache coherence without needing to significantly alter the SoC design and validation effort beyond the single processor design. With multiprocessing offering greater performance at lower frequencies than comparable single processor solutions, the unique features of the MPCore bring significant cost savings to system designers, while maintaining full compatibility with existing EDA tools and flows resulting in reduced time-to-market and total design costs.

Supporting the ARM11 microarchitecture, ARM11 MPCore designs can integrate software and operating system that are available for any ARM applications processor. Further, the ability to enable cache coherence between multiple processor brings both enhanced performance in existing multiple processor design and also enables the scalable performance of multiprocessing be access by software written using the increasingly popular threaded programming module and symmetric multiprocessor (SMP) aware operating systems.

Linux 2.6 is available for the ARM11 MPCore and provides full dynamic load balancing of applications and threads across the available processors while offering up to a 75% reduction in average power consumed when using the ARM11 MPCore benefit of being able to turn off processors during idol periods. This same low power solution also offers an aggregate peak performance of up to 2600 Dhrystone MIPS from a 130 nm TSMC process.

The ARMv6 architecture in an ARM11 applications processor has support for SIMD media extensions for next-generation rich multimedia and convergent devices and ARM Jazelle® Java acceleration. The ARM11 MPCore also features configurable over caches, the 64-bit AMBA AXI interface, an optional Vector Floating Point coprocessor per processor, private timers and a fully programmable interrupt distribution.

Supporting two levels of Adaptive Shutdown, unused processor within the ARM11 MPCore can have their clock and power independently isolated giving control over both dynamic and leakage power consumption. With a single core consuming as little as 0.49 mW/MHz from a generic 130m process – this plus the ability to control dynamically the frequency and voltage, the ARM11 MPCore can be considered for all power conscious high performance application processors.

Features

Configurable

Sizing of both data and instruction cache to 16K, 32K or 64K bytes across each processor.
Either dual or single 64-bit AMBA 3.0 AXI system bus allowing rapid and flexibility during SoC design
Optional integrated vector floating point unit
Up to 255 independent software directed interrupts

Efficient processing

Rich ARMv6 architecture-based instruction set architecture
Supports ARM Thumb® and Jazelle® instruction sets
ARM DSP and SIMD media processing extensions delivering up to 2x performance for video processing

Energy Efficient

Low power system with gate level shut down of unused resources
Support for dynamic voltage and frequency scaling
Ability to shutdown processors providing up to 85% energy saving on both dynamic and static energy usage

High performance memory

Cache allocation on both writes and read miss
Intelligent merging write buffer with full forwarding
Cork-screw cache arrangement for single cycle allocation and eviction
Support for cache-2-cache transfers

Simple design integration

Supported by the ARM Synopsys Reference Methodology
Integration of the essential system components provides to reduce the complexity and risk associated with porting OS
Single SoC instantiation of multiple processors