English
Creating multi-standard, multi-resolution video engines using configurable processors
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
By Sumit Gupta, Product Marketing Manager, Tensilica Inc.September 15, 2006 -- videsignline.com
Customize the processor to your video application by creating instructions, register files, functional units and interfaces that accelerate the processing.
The explosive growth of consumer electronics and, specifically, handheld devices such as cellular phones, PDAs, and portable media players (PMPs) has drastically changed the requirements placed on the end-silicon providers. These silicon providers can no longer design ICs that are targeted at only one or two multimedia codecs or wireless standards. Consumers expect their devices to play media from different sources, coded using different standards, and downloaded using a variety of different wireless standards. Therefore, a new, more flexible design approach must be taken that provides for easy adoption of new media standards. In this article, we focus on the challenges and opportunities for video decoder and encoder engines.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Flexible Embedded Processors for Developing Multi-Standard OFDM Broadcast Receivers
- Configurable Processors for Video Processing SOCs
- Creating Domain Specific Processors Using Custom RISC-V ISA Instructions
- Understanding in-loop filtering in the HEVC video standard
- Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)