English
How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)
By Roger Seaman, Xilinx
September 20, 2006 -- pldesignline.com
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.
September 20, 2006 -- pldesignline.com
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Xilinx, Inc. Hot IP
Related Articles
- How to power FPGAs with Digital Power Modules
- Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs
- How to reduce power consumption in CPLD designs with power supply cycling
- How to analyze and reduce power using Libero IDE
- Tips on using CPLDs to reduce system processor power consumption
New Articles
- Hardware-Assisted Verification: The Real Story Behind Capacity
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- SoC design: What's next for NoCs?
- How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
- Synopsys Foundation IP Enabling Low-Power AI Processors
Most Popular
- System Verilog Assertions Simplified
- Hardware-Assisted Verification: The Real Story Behind Capacity
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- I2C Interface Timing Specifications and Constraints