PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N4P. N5 , N6
High-definition video scaler ASIC development from FPGA
videsignline.com, September 29, 2006
How a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.
Consumers are buying ever larger numbers of liquid crystal displays (LCD), plasma and digital light processing (DLP) based systems. As digital displays continue to offer higher resolution capabilities, high quality video scaling is becoming a key feature for the new generation of high definition video sources.
This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology. The Anchor Bay Technology application targets the consumer market space for high-definition video sources (for example, HD-DVD and Blu-ray players). Achieving quick time-to-market was critical for the success of the project, in addition to beating competitive products in cost, features and ease-of-use. An FPGA prototype was used for at-speed verification of all functionality, especially image quality enhancements.
E-mail This Article | Printer-Friendly Page |
Related Articles
- How to implement a high-definition video design framework for FPGAs
- High Definition, Low Bandwidth -- Implementing a high-definition H.264 codec solution with a single Xilinx FPGA
- A configurable FPGA-based multi-channel high-definition Video Processing Platform
- Generating High Speed CSI2 Video by an FPGA
- Designing a high-definition FPGA-based graphics controller