How to design and verify mixed-signal FPGAs

A 'smart' system design and verification flow for mixed-signal FPGAs helps digital designers overcome the complexities of the analog domain.

By Michael Mertz and Venkatesh Narayanan, Actel
October 04, 2006 -- pldesignline.com

In order to meet the market's increasing demands for higher-performance functionality, smaller system form factors, and the reduction of cost and power, system designers are integrating higher levels of mixed-signal functionality into their system-on-chip (SoC) designs.

As the number of mixed-signal components in these SoC designs increases, basic functional verification becomes critical for early silicon success. Without this, system designers will spend millions of dollars on silicon re-spins, waste precious design and verification resources and quite possibly miss their market window.

Luckily, system designers today have more choices than in the past. It is no longer necessary when designing a mixed-signal system to be limited to mixed-signal ASICs, analog MCUs or discrete components. Mixed-signal FPGAs add a new dimension to the system integration puzzle, improving aspects of system integration, such as total system cost, reliability, reconfigurability, time to market, etc. At its core, this new paradigm – the "programmable system chip" (PSC) – integrates FPGA gates, embedded flash and analog functionality into a single programmable device, offering an ideal low cost path with true programmability, and with which system designers can rapidly design and develop their complex mixed-signal systems.

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