Multi-core MPEG-4 video encode partitioning
By Laurent Bonetto, Ram Natarajan, and Dr. R K Singh, Cradle Technologies
October 06, 2006 -- videsignline.com
Partitioning video processing algorithms onto multi-core architectures has been researched for decades, and over this time several techniques of varying efficiency have been developed to divide up the work among the processors. Let's take a closer look at some of these techniques, and see how video processing poses unique challenges to the multi-core processor.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- MPEG-4 system layer and A/V containers for wireless video
- MPEG-4 encoder on an embedded parallel DSP
- MPEG-4 is accelerated and footprint reduced by use of a configurable processor core
- Stepping through the processing requirements for MPEG-4
- SoC Configurable Platforms -> Adaptable computing right for MPEG-4
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution