English
Multi-core MPEG-4 video encode partitioning
Partitioning a video-encoding algorithm onto a multi-core architecture can utilize a variety of techniques, including data partitioning and pipelining. Cradle Technologies explains them, and how to do MPEG-4 Baseline Profile implementation on their multi-core CT3600 processor family.
By Laurent Bonetto, Ram Natarajan, and Dr. R K Singh, Cradle Technologies
October 06, 2006 -- videsignline.com
Partitioning video processing algorithms onto multi-core architectures has been researched for decades, and over this time several techniques of varying efficiency have been developed to divide up the work among the processors. Let's take a closer look at some of these techniques, and see how video processing poses unique challenges to the multi-core processor.
By Laurent Bonetto, Ram Natarajan, and Dr. R K Singh, Cradle Technologies
October 06, 2006 -- videsignline.com
Partitioning video processing algorithms onto multi-core architectures has been researched for decades, and over this time several techniques of varying efficiency have been developed to divide up the work among the processors. Let's take a closer look at some of these techniques, and see how video processing poses unique challenges to the multi-core processor.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- MPEG-4 system layer and A/V containers for wireless video
- MPEG-4 encoder on an embedded parallel DSP
- MPEG-4 is accelerated and footprint reduced by use of a configurable processor core
- Stepping through the processing requirements for MPEG-4
- SoC Configurable Platforms -> Adaptable computing right for MPEG-4
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)