Integrating 'hard' IP into a system-on-chip
(10/16/2006 9:00 AM EDT)
The integration of "hard" intellectual property blocks--those delivered as GDSII databases--lets system designers focus on their core competency by outsourcing certain blocks that previously had to be developed internally. Consequently, purchasing and integrating hard IP blocks is becoming a way of life for SoC designers. Off-the-shelf IP blocks are available for almost every function--from A/D converters to ZigBee transceivers.
Selecting a quality IP supplier is a top concern in yielding a successful IP integration. To that end, the Virtual Socket Interface Alliance and the Fabless Semiconductor Association are working with companies to develop a standard, objective quality metric for hard IP blocks and their suppliers.
During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiences, from the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations.
E-mail This Article | Printer-Friendly Page |
Related Articles
- How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time
- The Hard Truth about System-on-Chip Designs
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- Case study of a complex video system-on-chip
- A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™