English
Speed up downconverter implementation with rapid prototyping
By Jamie Bowman, Daniel Garca-Als, and Garrey Rice of Steepest Ascent Ltd.
November 13, 2006 -- dspdesignline.com
Using the right EDA tools, performance can be simulated, analyzed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation.
Digital downconversion of IF (Intermediate Frequency) signals is usually performed using dedicated hardware operating at high sampling rates. A downconverter typically takes the form of an integrated circuit with some flexible functionality in order to meet the requirements of a broad range of receiver designs.
These days, an entire digital receiver can be implemented on an FPGA or custom ASIC so that downconversion, synchronization and baseband processing are all contained within the same physical device. As a result, the entire design—including the downconversion stages—can be customized and optimized for the end application.
In this article, we demonstrate how DSP design and synthesis tools (such as HDL Design Studio 3 (HDS3) for SystemVue) can be used for rapid prototyping and implementation of downconverter hardware.
An example is used to show how a downconverter can be quickly designed and constructed from the appropriate set of DSP components, simulated, and then instantly converted to HDL code for synthesis and FPGA implementation.
DDC design
An important part of receiver design is the implementation of the Digital Downconverter (DDC), which takes a digital signal centered at an intermediate frequency (IF) and shifts it down to baseband, filtering noise and unwanted components in the process.
The design choices made will greatly affect the computational complexity of the final design. Therefore, customization and optimization of the DDC design, together with the appropriate choice of filtering and downsampling structures is of paramount importance to produce a design of reasonable size to implement on a FPGA or custom ASIC. Software tools can help in the process of migrating from a floating point model of the system under consideration towards an optimized fixed point model, allowing designers to quickly translate high-level behavioral models to RTL. Testbenches, clock, and control signals are automatically produced.
In this article we present the full design process of a DDC, from a floating point simulation system in Agilent's SystemVue, to generic HDL code generation using HDS3.
Toolkit
SystemVue, from Agilent Technologies, is a system-level design environment for development, simulation, and analysis. It has an intuitive block level design interface with extensive model libraries of digital signal processing components, modulation standards, and adaptive control elements.
SystemVue has been designed to speed communications, DSP, and RF analog system design. Furthermore, it provides a comprehensive set of analysis tools for exploring model behavior and stability. SystemVue is also capable of working with floating-point data as well as different fixed-point data types, thus making it suitable for bit-true system design targeting DSPs, FPGAs, and ASICs.
Hardware Design Studio 3 (HDS3) by Steepest Ascent Ltd. provides automatic HDL generation capabilities to Agilent's SystemVue. HDS3 has two main components: FXP-Lib: Is a library of fixed point behavioural blocks or tokens for different DSP components. These tokens are fully parameterisable bit-true and cycle accurate. FXP-Lib: also provides numerical analysis and optimisation. Some of the blocks included in this library are: multipliers, adders, dividers, square rooters, shifters, filters, gates, look up tables, re-samplers, etc.
HDL generation unit: this transparent unit generates generic HDL associated to the model built in SystemVue using FXP-Lib. The appropriate clock and control signals are also automatically generated here. A test-bench is also produced, allowing for simulation and verification of the generated HDL if desired. This HDL is generic and can target platforms from any manufacturer. Moreover, and in order to increase flexibility it is also hand edited, giving the designer full control at every stage.
HDS3 has been designed to assist in all the stages of the system design process: from floating point algorithm performance verification to automatic HDL generation, including migration to fixed point, optimization and numerical stability analysis.
November 13, 2006 -- dspdesignline.com
Using the right EDA tools, performance can be simulated, analyzed and design characteristics automatically converted to generic HDL code appropriate for synthesis and FPGA implementation.
Digital downconversion of IF (Intermediate Frequency) signals is usually performed using dedicated hardware operating at high sampling rates. A downconverter typically takes the form of an integrated circuit with some flexible functionality in order to meet the requirements of a broad range of receiver designs.
These days, an entire digital receiver can be implemented on an FPGA or custom ASIC so that downconversion, synchronization and baseband processing are all contained within the same physical device. As a result, the entire design—including the downconversion stages—can be customized and optimized for the end application.
In this article, we demonstrate how DSP design and synthesis tools (such as HDL Design Studio 3 (HDS3) for SystemVue) can be used for rapid prototyping and implementation of downconverter hardware.
An example is used to show how a downconverter can be quickly designed and constructed from the appropriate set of DSP components, simulated, and then instantly converted to HDL code for synthesis and FPGA implementation.
DDC design
An important part of receiver design is the implementation of the Digital Downconverter (DDC), which takes a digital signal centered at an intermediate frequency (IF) and shifts it down to baseband, filtering noise and unwanted components in the process.
The design choices made will greatly affect the computational complexity of the final design. Therefore, customization and optimization of the DDC design, together with the appropriate choice of filtering and downsampling structures is of paramount importance to produce a design of reasonable size to implement on a FPGA or custom ASIC. Software tools can help in the process of migrating from a floating point model of the system under consideration towards an optimized fixed point model, allowing designers to quickly translate high-level behavioral models to RTL. Testbenches, clock, and control signals are automatically produced.
In this article we present the full design process of a DDC, from a floating point simulation system in Agilent's SystemVue, to generic HDL code generation using HDS3.
Toolkit
SystemVue, from Agilent Technologies, is a system-level design environment for development, simulation, and analysis. It has an intuitive block level design interface with extensive model libraries of digital signal processing components, modulation standards, and adaptive control elements.
SystemVue has been designed to speed communications, DSP, and RF analog system design. Furthermore, it provides a comprehensive set of analysis tools for exploring model behavior and stability. SystemVue is also capable of working with floating-point data as well as different fixed-point data types, thus making it suitable for bit-true system design targeting DSPs, FPGAs, and ASICs.
Hardware Design Studio 3 (HDS3) by Steepest Ascent Ltd. provides automatic HDL generation capabilities to Agilent's SystemVue. HDS3 has two main components: FXP-Lib: Is a library of fixed point behavioural blocks or tokens for different DSP components. These tokens are fully parameterisable bit-true and cycle accurate. FXP-Lib: also provides numerical analysis and optimisation. Some of the blocks included in this library are: multipliers, adders, dividers, square rooters, shifters, filters, gates, look up tables, re-samplers, etc.
HDL generation unit: this transparent unit generates generic HDL associated to the model built in SystemVue using FXP-Lib. The appropriate clock and control signals are also automatically generated here. A test-bench is also produced, allowing for simulation and verification of the generated HDL if desired. This HDL is generic and can target platforms from any manufacturer. Moreover, and in order to increase flexibility it is also hand edited, giving the designer full control at every stage.
HDS3 has been designed to assist in all the stages of the system design process: from floating point algorithm performance verification to automatic HDL generation, including migration to fixed point, optimization and numerical stability analysis.
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