Practical Applications of Statistical Static Timing Analysis
(12/18/2006 10:19 AM EST) -- EE Times
Introduction
As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, which threatens to negate many of the benefits that smaller process geometries offer. Static timing analysis (STA) cannot properly account for the variability inherent in semiconductor processes, making exaggerated pessimism a necessary evil. Process variation " which at 90nm and above had a manageable impact on delay " has a much more dramatic effect as process geometries shrink. The reason this occurs is that process control becomes more difficult at smaller process nodes. Even if the amount of variation remained the same as in previous generations, it will account for a greater percentage of process geometries as they get smaller.
For instance, a 0.01ìm variation at the 1um process node is only 1% of the nominal. However, the same 0.01ìm variation at the 65nm process node is greater than 15% of the nominal. In traditional STA, this variability is accounted for by introducing more aggressive gross guard-band and new analysis corners to model different process and environmental variation combinations over multiple analysis runs. As the number of scenarios increases, the number of possible corners can increase greatly, making design convergence exceedingly difficult while straining resources, increasing costs, and negatively impacting schedule.
Statistics is emerging as the most likely vehicle to carry the industry forward into the future of timing analysis. Using a statistical approach it will be possible to break beyond the barriers of case analysis and begin to holistically model the factors affecting process variation in a single analysis run. This will not only obviate the need for corners but remove much of their inherent pessimism. The results will be in the form of a probability density function (PDF) " for instance a normal Gaussian distribution " which will indicate the probability of failure for a given timing slack, rather than the traditional slack number. This enables designers and management to evaluate parametric yield for a desired performance target " a key facet of Statistical Static Timing Analysis (SSTA).
E-mail This Article | Printer-Friendly Page |
Related Articles
- Static timing analysis: bridging the gap between simulation and silicon
- Cell model creation for statistical timing analysis
- Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis
- Five steps to reliable, low-cost, bug-free software with static code analysis
- Using static analysis to detect coding errors in open source security-critical server applications
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone