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Top 10 methods for ASIC power minimization -- Part 2
By Andreas Olofsson, Analog Devices
January 10, 2007 -- powermanagementdesignline.com
This last part describes five effective implementation-level low-power techniques for ASIC power minimization.
This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on five effective implementation level low power techniques.
January 10, 2007 -- powermanagementdesignline.com
This last part describes five effective implementation-level low-power techniques for ASIC power minimization.
This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on five effective implementation level low power techniques.
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