English
Top 10 methods for ASIC power minimization -- Part 2
By Andreas Olofsson, Analog Devices
January 10, 2007 -- powermanagementdesignline.com
This last part describes five effective implementation-level low-power techniques for ASIC power minimization.
This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on five effective implementation level low power techniques.
January 10, 2007 -- powermanagementdesignline.com
This last part describes five effective implementation-level low-power techniques for ASIC power minimization.
This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on five effective implementation level low power techniques.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Top 10 methods for ASIC power minimization -- Part 1
- Top 10 Tips for Success with Formal Analysis - Part 2
- Shift Power Reduction Methods and Effectiveness for Testability in ASIC
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Top 10 Tips for Success with Formal Analysis - Part 3
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)