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How to achieve faster compile times in high-density FPGAs
By Phil Simpson and Ajay Jagtiani, Altera
January 17, 2007 -- pldesignline.com
With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times.
Over the last eight years there has been a 30× increase in logic density and memory bits in FPGA devices. The largest FPGAs – such as the recently announced Stratix III EP3SL340 from Altera – contain up to 338,000 equivalent logic elements (LEs) and more than 17 Mbits of embedded memory.
This rapid increase in logic density translates to an even larger increase in computing requirements for design compilation and place and route. Unfortunately, CPU speed has only increased by a factor of 11× during the same period. With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times and allow them to iteratively and efficiently debug, add features, and close timing. This article presents a three-stage methodology to increase productivity for engineers designing with high-end FPGAs.
January 17, 2007 -- pldesignline.com
With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times.
Over the last eight years there has been a 30× increase in logic density and memory bits in FPGA devices. The largest FPGAs – such as the recently announced Stratix III EP3SL340 from Altera – contain up to 338,000 equivalent logic elements (LEs) and more than 17 Mbits of embedded memory.
This rapid increase in logic density translates to an even larger increase in computing requirements for design compilation and place and route. Unfortunately, CPU speed has only increased by a factor of 11× during the same period. With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times and allow them to iteratively and efficiently debug, add features, and close timing. This article presents a three-stage methodology to increase productivity for engineers designing with high-end FPGAs.
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