Improve performance and reduce power consumption in mixed-signal designs
February 14, 2007 -- rfdesignline.com
Designing high-reliability satellite communications systems is perhaps the most challenging mixed-signal design task. In addition to withstanding a wide range of temperatures and radiation, these systems also have to offer unprecedented levels of performance and reliability. Once the domain of only the military, space applications are now also fully entrenched in commercial markets, so cost and size have become key drivers for devices and components used in these applications as well. And, because of the lack of a ready power supply, one of the greatest concerns for satellite communications designers may be power consumption.
As a result, satellite system designers need devices with high levels of design flexibility and performance combined with low power consumption. By constructing their designs with devices built using UltraCMOS™ technology, a cost-effective silicon on insulator (SOI) technology on a sapphire substrate, they can satisfy design needs that could not be met with traditional GaAs and bulk CMOS alternatives.
Phase locked loops (PLLs), intermediate frequency (IF) integrated subsystems, and prescalers are some of the major mixed-signal (RF and digital) devices now being used in space applications. When implemented in UltraCMOS, they can lead to the design of lighter, smaller, higher-performing, lower-cost satellite systems that cost less to launch.
E-mail This Article | Printer-Friendly Page |
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)