English
How to map the H.264/AVC video standard onto an FPGA fabric
By Wilson Chung, Xilinx Inc.
March 02, 2007 -- dspdesignline.com
Despite its promise of improved coding efficiency over existing standards, H.264/AVC still presents engineering challenges.
It incorporates the most significant changes and algorithmic discontinuities in the evolution of video coding standards since the introduction of H.261. As a result, to achieve a real-time H.264/ AVC encoding solution, multiple FPGAs and programmable DSPs are often used.
To illustrate the computational complexity required, let's explore the typical runtime-cycle requirements of the H.264/AVC encoder based on the software model provided by the Joint Video Team (JVT). Using Intel VTune software running on a Pentium III 1GHz CPU with 512Mbytes of memory, achieving H.264/AVC SD with a main profile encoding solution would require about 1,600 billions of operations per second.
March 02, 2007 -- dspdesignline.com
Despite its promise of improved coding efficiency over existing standards, H.264/AVC still presents engineering challenges.
It incorporates the most significant changes and algorithmic discontinuities in the evolution of video coding standards since the introduction of H.261. As a result, to achieve a real-time H.264/ AVC encoding solution, multiple FPGAs and programmable DSPs are often used.
To illustrate the computational complexity required, let's explore the typical runtime-cycle requirements of the H.264/AVC encoder based on the software model provided by the Joint Video Team (JVT). Using Intel VTune software running on a Pentium III 1GHz CPU with 512Mbytes of memory, achieving H.264/AVC SD with a main profile encoding solution would require about 1,600 billions of operations per second.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Xilinx, Inc. Hot IP
Related Articles
- Emerging H.264 standard supports broadcast video encoding
- H.264/AVC HDTV Motion Compensation Soft IP
- Tutorial: The H.264 Scalable Video Codec (SVC)
- Multi-chip architectures partition H.264 tasks to achieve high-quality video
- H.264 "zero" latency video encoding and decoding for time-critical applications
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- CANsec: Security for the Third Generation of the CAN Bus
- Memory Testing - An Insight into Algorithms and Self Repair Mechanism
- Last-Time Buy Notifications For Your ASICs? How To Make the Most of It