The basics of HD H.264 and next-generation encoding
March 07, 2007 -- digitaltvdesignline.com
Video compression is a complex, compute-intensive task with numerous filtering and matrix operations. Current MPEG2 video codec chips have built-in DSPs, or special VLIW engines, and some hard-coded functionality to compress video in real-time. However, as the industry moves to high definition (HD) encoding, there is six times as much data to process as standard definition (SD), and the H.264/ AVC compression standard is greater than five times as complex as MPEG2, due to the large number of compression tools and options in AVC that can be used to compress a superlative picture at half the bit rate of MPEG2.
Broadcast equipment manufacturers developing new encoding products have to address different application requirements including those for the rapidly emerging IPTV segment. Encoding solutions must not only deliver high video quality and a low bit rate, but they should also be adaptable to the feature needs of the quickly proliferating range of video platforms. There are several solutions available to meet the challenges of HD video encoding, including PC platforms, FPGAs, dedicated ASIC/System on-chip codecs, and DSPs. We discuss the benefits and costs of each of these solutions, and draw on Telairity's experience in developing its H.264 HD real-time encoders to highlight the importance of programmable architectures for encoding solutions that deliver long-haul viability.
E-mail This Article | Printer-Friendly Page |
Related Articles
- H.264 "zero" latency video encoding and decoding for time-critical applications
- Meeting the Challenge of Real-Time Video Encoding: Migrating From H.263 to H.264
- Emerging H.264 standard supports broadcast video encoding
- H.264/AVC HDTV Motion Compensation Soft IP
- H.264 encoder design using Application Engine Synthesis
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)