English
Hardware and software don't matter
By Kenton Williston
April 16, 2007 -- dspdesignline.com
The typical DSP design process has three basic elements: Algorithm design, hardware design, and software design. Similarly, most DSP engineers think of themselves as belonging to one of three groups: Algorithm designers, hardware designers, or software designers.
This division of labor causes problems. For one thing, it creates a "thought gap" between the engineering groups: Algorithm designers rarely understand how the hardware works, the hardware designers rarely understand how software development works, and so on. In addition, each group tends to limit its thinking to its own area of specialization. For example, software designers don't want to worry about hardware design; they just want a hardware platform that works. This narrow thinking hinders the groups from aiding each other. Perhaps worst of all, each group uses different tools, languages, etc. As a result, miscommunication between the groups is common.
April 16, 2007 -- dspdesignline.com
The typical DSP design process has three basic elements: Algorithm design, hardware design, and software design. Similarly, most DSP engineers think of themselves as belonging to one of three groups: Algorithm designers, hardware designers, or software designers.
This division of labor causes problems. For one thing, it creates a "thought gap" between the engineering groups: Algorithm designers rarely understand how the hardware works, the hardware designers rarely understand how software development works, and so on. In addition, each group tends to limit its thinking to its own area of specialization. For example, software designers don't want to worry about hardware design; they just want a hardware platform that works. This narrow thinking hinders the groups from aiding each other. Perhaps worst of all, each group uses different tools, languages, etc. As a result, miscommunication between the groups is common.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)