English
Hardware and software don't matter
By Kenton Williston
April 16, 2007 -- dspdesignline.com
The typical DSP design process has three basic elements: Algorithm design, hardware design, and software design. Similarly, most DSP engineers think of themselves as belonging to one of three groups: Algorithm designers, hardware designers, or software designers.
This division of labor causes problems. For one thing, it creates a "thought gap" between the engineering groups: Algorithm designers rarely understand how the hardware works, the hardware designers rarely understand how software development works, and so on. In addition, each group tends to limit its thinking to its own area of specialization. For example, software designers don't want to worry about hardware design; they just want a hardware platform that works. This narrow thinking hinders the groups from aiding each other. Perhaps worst of all, each group uses different tools, languages, etc. As a result, miscommunication between the groups is common.
April 16, 2007 -- dspdesignline.com
The typical DSP design process has three basic elements: Algorithm design, hardware design, and software design. Similarly, most DSP engineers think of themselves as belonging to one of three groups: Algorithm designers, hardware designers, or software designers.
This division of labor causes problems. For one thing, it creates a "thought gap" between the engineering groups: Algorithm designers rarely understand how the hardware works, the hardware designers rarely understand how software development works, and so on. In addition, each group tends to limit its thinking to its own area of specialization. For example, software designers don't want to worry about hardware design; they just want a hardware platform that works. This narrow thinking hinders the groups from aiding each other. Perhaps worst of all, each group uses different tools, languages, etc. As a result, miscommunication between the groups is common.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
Most Popular
- System Verilog Assertions Simplified
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)