English
Floating- to fixed-point MATLAB algorithm conversion for FPGAs
By Tom Hill, Xilinx
June 04, 2007 -- dspdesignline.com
In a recent survey conducted by AccelChip Inc. (recently acquired by Xilinx), 53% of the respondents identified floating- to fixed-point conversion as the most difficult aspect of implementing an algorithm on an FPGA (Figure 1).
Figure 1. AccelChip DSP design challenges survey.
June 04, 2007 -- dspdesignline.com
In a recent survey conducted by AccelChip Inc. (recently acquired by Xilinx), 53% of the respondents identified floating- to fixed-point conversion as the most difficult aspect of implementing an algorithm on an FPGA (Figure 1).
Figure 1. AccelChip DSP design challenges survey.
Although MATLAB is a powerful algorithm development tool, many of its benefits are reduced during the fixed-point conversion process. For example, new mathematical errors are introduced into the algorithm because of the reduced precision of the fixed-point arithmetic. You must rewrite code to replace high-level functions and operators with low-level models that reflect the actual hardware macro-architecture. And simulation run times can be as much as 50 times longer. For these reasons, MATLAB, the overwhelming choice for algorithm development, is often abandoned in favor of C/C++ for fixed-point modeling.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Xilinx, Inc. Hot IP
Related Articles
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution