English
Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1
By Jay Johnson, Atmel Corp.
Jun 13 2007 (18:15 PM), Embedded.com
Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.
This approach provides for a silicon-efficient design, but is expensive because it requires a full mask set. Mask costs increase sharply with shrinking process technology or feature size.
Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthy design time associated with standard cell ASICs puts them out of reach for many products. In fact, in applications such as MP3 players or cell phones, the technology evolves so rapidly that the next generation product must be launched every six months -- about half the time required to implement a cell-based ASIC.
Jun 13 2007 (18:15 PM), Embedded.com
Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.
This approach provides for a silicon-efficient design, but is expensive because it requires a full mask set. Mask costs increase sharply with shrinking process technology or feature size.
Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthy design time associated with standard cell ASICs puts them out of reach for many products. In fact, in applications such as MP3 players or cell phones, the technology evolves so rapidly that the next generation product must be launched every six months -- about half the time required to implement a cell-based ASIC.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Bridging the gap between custom ASICs and ARM-based MCUs
- FPGAs tackle microcontroller tasks: Part 1 - Application growth strains architecture and ASICs
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
- Efficient analysis of CDC violations in a million gate SoC, part 1
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution