English
FPGA-based coprocessors simplify ASIC emulation
By Richard Povey, DRC Computer Corp.
Jul 2 2007 (9:00 AM), Embedded.com
With compressed time lines and intense pressure to get it right the first time, ASIC emulation has become an increasingly critical part of the design process. Designers have historically had few good options for emulating ASICs, however. Now, many are turning to a new tool: FPGA-based coprocessors. These reconfigurable coprocessors are allowing designers to eliminate many of the issues associated with conventional ASIC emulation and deliver more accurate designs more quickly and with less effort.
A coprocessor approach also allows for much faster startup times than building hardware from scratch. In addition, because the reconfigurable processor has a tightly coupled, low-latency link with the CPU, designers can exercise the emulated hardware they create at very high speeds--orders of magnitude faster than a software simulator.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems
- How to simplify power design development and evaluation for FPGA-based systems
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
- Designing a high-definition FPGA-based graphics controller
- Designing an FPGA-based graphics controller
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware