English
Defining standard Debug Interface Socket requirements for OCP-compliant multicore SoCs: Part 2
By Neal Stollon, HDL Dynamics, Bob Uvacek, Pixelworks, and Gilbert Laurenti, Texas Instruments
Jul 16 2007 (0:05 AM), Embedded.com
As discussed in Part 1 in this series, in the same way the OCP data socket is a superset for the different bus interfaces and data structures, an OCP debug socket will provide a superset of the debug solutions based on standardized libraries of debug IP blocks that interact with the debug sockets signals. This allows the following:
Jul 16 2007 (0:05 AM), Embedded.com
As discussed in Part 1 in this series, in the same way the OCP data socket is a superset for the different bus interfaces and data structures, an OCP debug socket will provide a superset of the debug solutions based on standardized libraries of debug IP blocks that interact with the debug sockets signals. This allows the following:
-
Signal level observation (bus and system trace) and control (triggering)
-
Consistent (multiple) processor software debugger and bus traffic observation interfaces
-
Special debug features for security islands, voltage islands, gated clock islands etc.
-
New classes of debug errors (which are different from system errors.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1
- Standard Debug Interface Socket Requirements For OCP-Compliant SoC
- Part 2: Opening the 5G Radio Interface
- Basics of the Cortex MCU Software Interface Standard: Part 1 - CMSIS Specification
- Hardware/software design requirements planning - Part 2: Decomposition using structured analysis
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)