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Defining standard Debug Interface Socket requirements for OCP-compliant multicore SoCs: Part 2
By Neal Stollon, HDL Dynamics, Bob Uvacek, Pixelworks, and Gilbert Laurenti, Texas Instruments
Jul 16 2007 (0:05 AM), Embedded.com
As discussed in Part 1 in this series, in the same way the OCP data socket is a superset for the different bus interfaces and data structures, an OCP debug socket will provide a superset of the debug solutions based on standardized libraries of debug IP blocks that interact with the debug sockets signals. This allows the following:
Jul 16 2007 (0:05 AM), Embedded.com
As discussed in Part 1 in this series, in the same way the OCP data socket is a superset for the different bus interfaces and data structures, an OCP debug socket will provide a superset of the debug solutions based on standardized libraries of debug IP blocks that interact with the debug sockets signals. This allows the following:
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Signal level observation (bus and system trace) and control (triggering)
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Consistent (multiple) processor software debugger and bus traffic observation interfaces
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Special debug features for security islands, voltage islands, gated clock islands etc.
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New classes of debug errors (which are different from system errors.
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