Self-timed interconnect enables true IP reuse

Silistix is no more in business

By David Lautzenheiser, Silistix
(07/25/2007 2:48 PM EDT)

Ask designers of complex chips to put together a short list of what would make their jobs simpler, and something that would appear on every list would be ways of making intellectual-property reuse faster and easier. Despite many claims from both third-party IP vendors and from internal IP development groups at chip companies that their IP is reusable from design to design with little or no rework or extra verification, this is simply not the case. Since every IP core "sees" a different environment in each unique design that employs it, chip designers have to expend considerable effort on each design to verify the IP's operation within it.

Many of the obstacles to true IP reusability can be traced to the coupling between the various IP cores on a chip, represented by the global clock-based connections used to provide intercore IP data flow. Replacing a clock-based bus system with self-timed logic to communicate among cores would eliminate many of the problems designers face when reusing IP in different systems-on-chip.

Almost all SoCs operate with a global clock that operates as a "heartbeat" to synchronize data flow among the different parts of the chip. The individual IP cores on the chip can operate at different frequencies; but to achieve certain levels of performance or to reduce power dissipation, all the individual IP "clock regions" must be synchronized to the master (global) clock, which also controls data flow on the buses between the cores. That imposes a relatively high degree of coupling among the various IP blocks on an SoC, resulting in differences among chips in how the IP is employed. Those differences adversely affect the reusability of IP from chip to chip. Between two chips that use the same piece of IP, any differences in system operation that affect how that IP communicates with other IP on the chip results in a designer's having to spend extra time to make sure that the IP works as expected on each chip. That dramatically reduces the benefits of reuse of that core.

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