English
IP/foundry ecosystem facilitates 45-nm process design
By Kurt Wolf, TSMC and Alexander Shubat, Virage Logic
(07/26/2007 4:49 PM EDT) -- EE Times
To overcome 45-nm process challenges, semiconductor intellectual property (IP) providers and foundries are collaborating to provide designers with a combination of design resources and manufacturing expertise focused on advanced process nodes. TSMC and Virage Logic are proactively collaborating on 45-nm process and IP development so designers can make best use of the growing IP-foundry ecosystem.
Many designers just completing tapeout for 65-nm and 55-nm process technologies are now well into 45-nm chip designs.
TSMC's 45-nm process technology and design ecosystem platform offers designers the combination of faster performance and lower active and standby power consumption, along with tools and support services to accelerate the design process.
The transition to 90-nm process technology resulted in the birth of the design-for-manufacture / design-for-yield (DFM/DFY) era and the focus on design parameters such as local variation, sub-threshold and gate leakage, and lifetime limiting electro-migration (EM) and negative bias temperature instability (NBTI) effects.
As test silicon was evaluated, it became obvious that in the deep sub-micron era, IP must be subjected to a stress environment that is much closer to the system-on-chip (SoC) use models. The test silicon strategy had to be significantly augmented.
(07/26/2007 4:49 PM EDT) -- EE Times
To overcome 45-nm process challenges, semiconductor intellectual property (IP) providers and foundries are collaborating to provide designers with a combination of design resources and manufacturing expertise focused on advanced process nodes. TSMC and Virage Logic are proactively collaborating on 45-nm process and IP development so designers can make best use of the growing IP-foundry ecosystem.
Many designers just completing tapeout for 65-nm and 55-nm process technologies are now well into 45-nm chip designs.
TSMC's 45-nm process technology and design ecosystem platform offers designers the combination of faster performance and lower active and standby power consumption, along with tools and support services to accelerate the design process.
The transition to 90-nm process technology resulted in the birth of the design-for-manufacture / design-for-yield (DFM/DFY) era and the focus on design parameters such as local variation, sub-threshold and gate leakage, and lifetime limiting electro-migration (EM) and negative bias temperature instability (NBTI) effects.
As test silicon was evaluated, it became obvious that in the deep sub-micron era, IP must be subjected to a stress environment that is much closer to the system-on-chip (SoC) use models. The test silicon strategy had to be significantly augmented.
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