English
Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
Analysis: Tensilica's D1 Video Engine
August 01, 2007 -- dspdesignline.com
Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it's one of four new dual-core "VDO" video engines from Tensilica. The 388VDO is the highest-performance member of the quartet and supports a variety of video codec standards at resolutions up to D1 (i.e., standard definition television). Target applications include chips for mobile handsets and personal media players.
The 388VDO incorporates two heterogeneous processor cores, each of which is configured to support different types of processing. One core supports 16- and 8-way SIMD operations and is optimized for the highly data-parallel processing that's characteristic of tasks like motion compensation and transforms; this core is called the "pixel processor." The other is optimized for the sequential processing needed for decision-making and bitstream unpacking; this core is called the "stream processor."
Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it's one of four new dual-core "VDO" video engines from Tensilica. The 388VDO is the highest-performance member of the quartet and supports a variety of video codec standards at resolutions up to D1 (i.e., standard definition television). Target applications include chips for mobile handsets and personal media players.The 388VDO incorporates two heterogeneous processor cores, each of which is configured to support different types of processing. One core supports 16- and 8-way SIMD operations and is optimized for the highly data-parallel processing that's characteristic of tasks like motion compensation and transforms; this core is called the "pixel processor." The other is optimized for the sequential processing needed for decision-making and bitstream unpacking; this core is called the "stream processor."
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution