Facilitating technology insertion in advanced wireless systems
By Lee Pucker, Spectrum Signal Processing
Aug 1 2007 (17:19 PM), Courtesy of Wireless Net DesignLine
The baseband or modem processing engines in many advanced wireless systems often include a variety of programmable "off-the-shelf" signal processing devices such as digital signal processors (DSPs) and field programmable gate arrays (FPGAs).
These devices tend to evolve following some variant of Moore's law, with new generations of devices incorporating new features and capabilities introduced every two to three years.
Original equipment manufacturers (OEMs) developing advanced wireless systems can take advantage of this trend to offer their customers cost-effective feature enhancements and upgrades in existing systems through technology insertion by replacing only the baseband processing engine while retaining other subsystems, such as the RF or control subsystems as is.
This article will explore the architectural requirements necessary to facilitate this manner of technology insertion in an advanced wireless system.
Part 1 of the article will examine the requirements on the baseband processing engine hardware architecture, and propose a software/firmware model for minimizing the cost to the OEM in moving from one generation of technology to the next by maximizing the reuse of intellectual property (IP) across roadmap products.
Part 2 of the article will present a real world example illustrating the efficacy of the proposed architectural models.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- Advanced Packaging and Chiplets Can Be for Everyone
- Optimal OTP for Advanced Node and Emerging Applications
- Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools
- The Role of Interconnection in the Evolution of Advanced Packaging Technology
- Utilization of Advanced Pytest Features
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow